Commits · d6d7f7b1d2639a06002779aed5dccf53fee20c6e · Roger Ferrer / llvm-epi · GitLab

Jul 06, 2023
- [AIX][XCOFF] print out the traceback info · d6d7f7b1
  zhijian authored Jul 06, 2023
  d6d7f7b1
- [CaptureTracking] Don't consider comparison of inbounds GEP with nonnull non-capturing · f3d0613d
  Nikita Popov authored Jun 29, 2023
  f3d0613d
- [X86] isTargetShuffleEquivalent - ensure the reference operands are vector types · a69ffd6c
  Simon Pilgrim authored Jul 06, 2023
  a69ffd6c
- [Mips] Replace OperandMatchResultTy with ParseStatus (NFC) · ab49d305
  Sergei Barannikov authored Jul 03, 2023
  ab49d305
- AMDGPU: Make SIFixVGPRCopies preserve everything · c70cae63
  Matt Arsenault authored Jul 01, 2023
  c70cae63
- AMDGPU: Fold out sign bit ops on frexp_exp · 8ee1cc82
  Matt Arsenault authored Jul 03, 2023
  8ee1cc82
- [SVE] Add isel for 32-bit add/sub(cntp()) -> incp/decp. · 90b83a6d
  Paul Walker authored Jul 03, 2023
  90b83a6d
- [BPF] Undo transformation for LICM.cpp:hoistMinMax() · 09feee55
  Eduard Zingerman authored Apr 11, 2023
  09feee55
- [DemandedBits] Print function name when printing analysis. · 99b3b8e5
  Florian Hahn authored Jul 06, 2023
  99b3b8e5
- [InstSimplify] Fold gep inbounds undef to undef instead of poison · 6c7fd723
  Nikita Popov authored Jun 30, 2023
  6c7fd723
- [AIX][TLS] Generate optimized local-exec access code sequence using X-Form loads/stores · 598cccea
  Amy Kwan authored Jun 30, 2023
  598cccea
- [LV] Consider if scalar epilogue is required in getMaximizedVFForTarget. · a0fcf84a
  Florian Hahn authored Jul 06, 2023
  a0fcf84a
- [llvm][Support] Deprecate llvm::writeFileAtomically API · 7aafea00
  Haojian Wu authored Jul 03, 2023
  7aafea00
- [X86] Fold BITOP(PACKSS(X,Z),PACKSS(Y,W)) --> PACKSS(BITOP(X,Y),BITOP(Z,W)) (REAPPLIED) · 3f7470c3
  Simon Pilgrim authored Jul 06, 2023
  3f7470c3
- [JITLink][RISCV] Move relax to PostAllocationPasses · 1e60ab0f
  Job Noorman authored Jul 06, 2023
  1e60ab0f
- [InstCombine] Transform (A > 0) | (A < 0) -> zext (A != 0) fold · bfb5d2e6
  XChy authored Jul 06, 2023
  bfb5d2e6
- [AMDGPU] Fix register class for a subreg in GCNRewritePartialRegUses. · 98aa8439
  Valery Pykhtin authored Jun 09, 2023
  98aa8439
- [LibCallsShrinkWrap] Set IsFPConstrained is true for creating quiet floating... · 893cc970
  Jim Lin authored Jul 06, 2023
  893cc970
- [LTO] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D123803 · 93e67248
  Fangrui Song authored Jul 05, 2023
  
  93e67248
- [XRay][AArch64] Implement __xray_ArgLoggerEntry · 9e7a052e
  Fangrui Song authored Jul 05, 2023
  
  9e7a052e
- AMDGPU: Remove add_dependencies calls from CMakeLists.txt · 62748e93
  Tom Stellard authored Jul 05, 2023
  62748e93
- [RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X)) · ee34fa00
  Craig Topper authored Jul 05, 2023
  ee34fa00
- [RISCV][NFC] Simplify uses of PatFrag binop_oneuse · a824b004
  Ben Shi authored Jul 04, 2023
  a824b004
- DAG: Implement soften float for ffrexp · e8ed6e35
  Matt Arsenault authored Jul 05, 2023
  e8ed6e35
- [RISCV][TableGen] Remove f32 from XLenFVT for RV32. · 9c4aa85e
  Craig Topper authored Jul 05, 2023
  9c4aa85e
- Revert "[PowerPC] Remove extend between shift and and" · 7cd9084c
  Nemanja Ivanovic authored Jul 05, 2023
  7cd9084c
Jul 05, 2023
- [llvm] A Unified LTO Bitcode Frontend · a1ca3af3
  Matthew Voss authored Jul 05, 2023
  a1ca3af3
- Revert "[X86] Fold BITOP(PACKSS(X,Z),PACKSS(Y,W)) --> PACKSS(BITOP(X,Y),BITOP(Z,W))" · 156913cb
  Arthur Eubanks authored Jul 05, 2023
  156913cb
- DAG: Fix dropping flags when widening unary vector ops · 20964c90
  Matt Arsenault authored Jun 14, 2023
  
  20964c90
- AMDGPU: Correctly lower llvm.exp.f32 · 54916662
  Matt Arsenault authored Jun 14, 2023
  54916662
- AMDGPU: Correctly lower llvm.exp2.f32 · ed556a1a
  Matt Arsenault authored Jun 14, 2023
  ed556a1a
- Weaken MFI Max Call Frame Size Assertion · 198df5f6
  Oskar Wirga authored Jul 05, 2023
  198df5f6
- AMDGPU: Always use v_rcp_f16 and v_rsq_f16 · 9c82dc6a
  Matt Arsenault authored Jun 30, 2023
  9c82dc6a
- [PowerPC] Remove extend between shift and and · a57236de
  Nemanja Ivanovic authored Jul 05, 2023
  a57236de
- [RISCV] Remove legacy TA/TU pseudo distinction for load instructions · 403261ea
  Philip Reames authored Jul 05, 2023
  403261ea
- AMDGPU: Correctly lower llvm.log.f32 and llvm.log10.f32 · 4e15f378
  Matt Arsenault authored Jun 11, 2023
  4e15f378
- [LV] Update generateInstruction to return produced value (NFC). · 2265bb06
  Florian Hahn authored Jul 05, 2023
  2265bb06
- [RISCV] Lower deinterleave2 intrinsics to vlseg2 · ea62fc79
  Luke Lau authored Jun 27, 2023
  ea62fc79
- [RISCV] Lower interleave2 intrinsics to vsseg2 · 70093fcf
  Luke Lau authored Jun 27, 2023
  70093fcf
- [SystemZ][z/OS] z/OS ADA codegen and emission · 163aad6b
  Yusra Syeda authored Jul 05, 2023
  163aad6b