Commits · e9569748def85a2f6bb8066e516a84e6933ef407 · Roger Ferrer / llvm-epi · GitLab

May 09, 2023
- [CodeGen][KCFI] Move cfi-type lowering to TargetLowering · e9569748
  Sami Tolvanen authored May 09, 2023
  e9569748
- [AArch64] Remove global constructors from AArch64Disassembler.cpp. · c1d94ea0
  Craig Topper authored May 09, 2023
  c1d94ea0
May 08, 2023
- Revert "[AArch64] Emit FNMADD instead of FNEG(FMADD)" · 4157625c
  Manoj Gupta authored May 07, 2023
  4157625c
May 05, 2023
- [AArch64] Extend fp64 top zeroing peephole to all instructions · 6e7840dd
  David Green authored May 05, 2023
  6e7840dd
- [AArch64] Handle vector with two different values · b18161d7
  Jingu Kang authored Apr 25, 2023
  b18161d7
- [AArch64] Emit FNMADD instead of FNEG(FMADD) · ea228bd0
  Matt Devereau authored May 05, 2023
  ea228bd0
- Revert "[AArch64] Emit FNMADD instead of FNEG(FMADD)" · f9ff2468
  Matt Devereau authored May 05, 2023
  f9ff2468
- [AArch64] Emit FNMADD instead of FNEG(FMADD) · caa95c24
  Matt Devereau authored May 04, 2023
  caa95c24
May 04, 2023
- MCInstrAnalysis: make GotPltSectionVA x86-32 specific · b05cd680
  Fangrui Song authored May 03, 2023
  b05cd680
May 03, 2023
- [AArch64] Add more efficient bitwise vector reductions. · 8e46ac36
  Sp00ph authored May 03, 2023
  8e46ac36
- [AArch64] Combine concat through rshrn · b96967ad
  David Green authored May 03, 2023
  b96967ad
May 02, 2023
- Split out `CodeGenTypes` from `CodeGen` for LLT/MVT · 5d71ec6e
  NAKAMURA Takumi authored Apr 17, 2023
  5d71ec6e
- Restore CodeGen/MachineValueType.h from `Support` · c1221251
  NAKAMURA Takumi authored Apr 11, 2023
  c1221251
- Restore CodeGen/LowLevelType from `Support` · 9cfeba5b
  NAKAMURA Takumi authored Apr 11, 2023
  9cfeba5b
- [AArch64] Add sign bits handling for vector compare nodes · 41549b53
  David Green authored May 02, 2023
  41549b53
Apr 29, 2023
- [SelectionDAG] Rename ADDCARRY/SUBCARRY to UADDO_CARRY/USUBO_CARRY (NFC) · e744e51b
  Sergei Barannikov authored Apr 29, 2023
  e744e51b
Apr 28, 2023
- [AArch64] Add preserve_all calling convention. · d75e70d7
  Daniel Kiss authored Apr 28, 2023
  d75e70d7
- [AArch64] Add support for efficient bitcast in vector truncate store. · cd68e17b
  Lawrence Benson authored Apr 28, 2023
  cd68e17b
- [AArch64][FastISel] Handle CRC32 intrinsics · ab21beac
  Alexis Engelke authored Apr 21, 2023
  ab21beac
- [hwasan] fix false positive when hwasan-match-all-tag flag is enabled and short granules are used · d961f66b
  Enna1 authored Apr 28, 2023
  d961f66b
Apr 27, 2023
- [IR][NFC] Change UndefMaskElem to PoisonMaskElem · d22edb97
  ManuelJBrito authored Apr 27, 2023
  d22edb97
- [AArch64][FastISel] Handle call with multiple return regs · 7751a914
  Alexis Engelke authored Apr 14, 2023
  7751a914
Apr 26, 2023
- [AArch64][SVE] Generate smull/umull instead of sve v2i64 mul · d340ef69
  David Green authored Apr 26, 2023
  d340ef69
- [InlineAsm][AArch64]Add backend support for flag output parameters · 9879e586
  Mingming Liu authored Apr 23, 2023
  9879e586
- [llvm] Replace None with std::nullopt in comments (NFC) · 1ca0cb71
  Kazu Hirata authored Apr 25, 2023
  1ca0cb71
Apr 25, 2023
- [AArch64][SME] NFC: Fix comment in enum class · 1675a14b
  Cullen Rhodes authored Apr 25, 2023
  
  1675a14b
- Move CodeGen/LowLevelType => CodeGen/LowLevelTypeUtils · d45fae60
  NAKAMURA Takumi authored Apr 23, 2023
  d45fae60
Apr 24, 2023
- [AArch64][DAGCombiner]: combine <2xi64> mul add/sub. · 23f2b865
  Hassnaa Hamdi authored Apr 20, 2023
  23f2b865
Apr 21, 2023
- Recommit "[AArch64] Fix incorrect `isLegalAddressingMode`" · 6c9066fe
  Momchil Velikov authored Apr 21, 2023
  6c9066fe
- [AArch64] Fix crash caused by performExtractVectorEltCombine on DUP nodes with float operands. · 872924fa
  Zain Jaffal authored Apr 21, 2023
  872924fa
- [CodeGen] Enable AArch64 SVE FCMLA/FCADD instruction generation in ComplexDeinterleaving · 6850bc35
  Igor Kirillov authored Apr 03, 2023
  6850bc35
Apr 20, 2023
- [AArch64] Improve fsh(l|r) cost modeling if 3rd arg is constant. · 3d3d8fef
  Zain Jaffal authored Apr 20, 2023
  3d3d8fef
- Revert "[AArch64] Fix incorrect `isLegalAddressingMode`" · ed7ada25
  Momchil Velikov authored Apr 20, 2023
  ed7ada25
- [AArch64] Make stack tagging compatible with SLH · 5e612bc2
  Kristof Beyls authored Apr 17, 2023
  5e612bc2
- [AArch64] Fix incorrect `isLegalAddressingMode` · 0827e2fa
  Momchil Velikov authored Apr 20, 2023
  0827e2fa
- [AArch64][CostModel] Make sext/zext free if folded into a masked load · afc2b7db
  David Sherwood authored Apr 05, 2023
  afc2b7db
Apr 19, 2023
- [AArch64][CodeGen] Allow vectors larger than hardware support to use SVE's... · 3e76d012
  Dinar Temirbulatov authored Apr 19, 2023
  3e76d012
- [AArch64] Remove dead tryMLAV64LaneV128 and tryMULLV64LaneV128 code. · 139f678c
  David Green authored Apr 19, 2023
  139f678c
- [DAGCombine][AArch64] Allow transformable to legal vectors to be used for MULH lowering. · e6096871
  Dinar Temirbulatov authored Apr 19, 2023
  e6096871
- [SLP]Fix cost estimation for buildvectors with extracts and/or constants. · 8cf0290c
  Alexey Bataev authored Apr 14, 2023
  8cf0290c