Commits · f12a5561b2cbfae384c9a31293938ee2acea79fd · Roger Ferrer / llvm-epi · GitLab

Jul 20, 2023
- [InstCombine] Fold binop of `select` and cast of `select` condition · f12a5561
  Antonio Frighetto authored Jul 05, 2023
  f12a5561
- [InstCombine] Introduce tests for D153963 · c9fd7ac3
  Antonio Frighetto authored Jul 20, 2023
  c9fd7ac3
- [test][llvm-reduce] Remove implicit-check-not in reduce-linkage.ll · 962a6fe5
  Arthur Eubanks authored Jul 20, 2023
  962a6fe5
- Revert "[MachineLICM] Handle Subloops" · 351b4c17
  Jingu Kang authored Jul 20, 2023
  351b4c17
- Revert "[IR] Mark add constant expressions as undesirable" · 9dc391e8
  Nikita Popov authored Jul 20, 2023
  9dc391e8
- [MachineLICM] Handle Subloops · 50dd383d
  Jingu Kang authored Jul 19, 2023
  50dd383d
- [ConstraintElim] Store the triple Pred + LHS + RHS in ReproducerEntry instead of CmpInst + Not · cce53249
  Yingwei Zheng authored Jul 20, 2023
  cce53249
- [RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC · 24bb36e5
  Craig Topper authored Jul 20, 2023
  24bb36e5
- [RISCV] Remove unused Opcode field from RVInst16. NFC · 09174c08
  Craig Topper authored Jul 20, 2023
  09174c08
- [RISCV] Order the RISCVInstrInfo*.td includes for standard extensions into logical groups. NFC · 8dacf55a
  Craig Topper authored Jul 20, 2023
  8dacf55a
- [AArch64] Reuse larger DUPLANE if available · 8bad7ad6
  Jingu Kang authored Jul 18, 2023
  8bad7ad6
- [FPEnv][RISCV] Correct strictfp tests. · 95c2d01d
  Kevin P. Neal authored Jul 20, 2023
  95c2d01d
- [MLIR][OpenMP][OMPIRBuilder] Use target triple to initialize `IsGPU` flag · 40340cf9
  Sergio Afonso authored Jun 01, 2023
  40340cf9
- [IVUsers] Check getExpr result in findAddRecForLoop. · 3ba3ea3c
  Florian Hahn authored Jul 20, 2023
  3ba3ea3c
- Implement -frecord-command-line for XCOFF integrated assembler path · 311abf5f
  Jake Egan authored Jul 20, 2023
  311abf5f
- [RISCV][NFC] Get rid of additional unneeded static_cast around RISCVSubtarget · cde5e428
  Alex Bradbury authored Jul 20, 2023
  cde5e428
- [IR] Mark add constant expressions as undesirable · f8a36d8c
  Nikita Popov authored Jul 20, 2023
  f8a36d8c
- [InstCombine] Avoid ConstantExpr::get() · 632594fc
  Nikita Popov authored Jul 20, 2023
  632594fc
- [RISCV][NFC] Use templated getSubtarget in RISCVExpandPseudo::runOnMachineFunction · 60152f19
  Alex Bradbury authored Jul 20, 2023
  60152f19
- [Statepoint] Use correct RegisterClass for spilling · e1aa4e7b
  Danila Malyutin authored Jul 20, 2023
  e1aa4e7b
- [X86] LowerTRUNCATE - use LowerTruncateVecPackWithSignBits for prefer-256 bit... · cc77da50
  Simon Pilgrim authored Jul 20, 2023
  cc77da50
- [AArch64] Update bswap cost test. NFC · 4f578e94
  David Green authored Jul 20, 2023
  4f578e94
- [LVI] Check ConstantFoldCompareInstOperands() failure (NFCI) · 781beb3d
  Nikita Popov authored Jul 20, 2023
  781beb3d
- [ConstantFolding] Update failure behavior documentation (NFC) · b846f439
  Nikita Popov authored Jul 20, 2023
  b846f439
- [LoongArch] Fix instruction definitions that were incorrectly specified input/output operands · 4a8cc738
  wanglei authored Jul 18, 2023
  4a8cc738
- [RISCV] Don't include X1 in the X0_PD register pair · 48a749e2
  Alex Bradbury authored Jul 20, 2023
  48a749e2
- [InstCombine] Avoid ConstantExpr::getAnd() (NFCI) · cdab6116
  Nikita Popov authored Jul 20, 2023
  cdab6116
- [gn build] Port a2160dd3 · dbb61955
  LLVM GN Syncbot authored Jul 20, 2023
  
  dbb61955
- [GIsel][AArch64] extend legalization of G_INSERT_VECTOR_ELT · 9d138bae
  Thorsten Schütt authored Jul 14, 2023
  9d138bae
- [TableGen][CodeEmitterGen] Avoid empty OpNum switches in getOperandBitOffset() · c05eff2f
  Ilya Leoshkevich authored Jul 20, 2023
  c05eff2f
- [DAG] ShrinkDemandedConstant - early-out for empty DemandedBits/Elts · 7567b72f
  Simon Pilgrim authored Jul 20, 2023
  7567b72f
- [DAG] hoistLogicOpWithSameOpcodeHands - ensure SIGN_EXTEND_INREG nodes have... · 697f6059
  Simon Pilgrim authored Jul 20, 2023
  697f6059
- [X86] Add test case showing incorrect and(sextinreg(v0,i2),sextinreg(v1,i5))... · f1cc7913
  Simon Pilgrim authored Jul 20, 2023
  f1cc7913
- [LV][AArch64] Fix reductions costs in strict-fadd-cost.ll. NFC · 2e0bf67d
  David Green authored Jul 20, 2023
  2e0bf67d
- [NFC][RISCV] Rewrite TableGen files using named arguments · 69fc6bf6
  Pengcheng Wang authored Jul 20, 2023
  69fc6bf6
- [gn build] Port 1c154bd7 · c49f2f39
  LLVM GN Syncbot authored Jul 20, 2023
  
  c49f2f39
- [gn build] Port 049d6a3f · ff3b624b
  LLVM GN Syncbot authored Jul 20, 2023
  
  ff3b624b
- [DAG][AArch64] Fix truncated vscale constant types · 0c41c59d
  David Green authored Jul 20, 2023
  0c41c59d
- [TableGen][CodeEmitterGen] Add support for querying operand bit offsets · 8b655e1f
  Ilya Leoshkevich authored Jul 20, 2023
  8b655e1f
- [TableGen] Support named arguments · 91ccbc6c
  Pengcheng Wang authored Jul 20, 2023
  91ccbc6c