Commits · fe05a0a3ddbf7fb54af9536331d39b138763e17a · Roger Ferrer / llvm-epi · GitLab

Nov 15, 2022
- [SDAG] avoid udiv/urem transform for vector/scalar type mismatches · fe05a0a3
  Sanjay Patel authored Nov 15, 2022
  fe05a0a3
- PEI should be able to use backward walk in replaceFrameIndicesBackward. · e05ce03c
  Alexander Timofeev authored Nov 04, 2022
  e05ce03c
- [GlobalISel] Remove semantic operand of G_IS_FPCLASS · ec893da9
  Serge Pavlov authored Nov 15, 2022
  ec893da9
Nov 14, 2022
- [MachineCSE] Allow CSE for instructions with ignorable operands · 11e86868
  Guozhi Wei authored Nov 14, 2022
  11e86868
- [ARM][CodeGen] Add support for complex deinterleaving · d52e2839
  Nicholas Guy authored Nov 14, 2022
  d52e2839
- [TableGen] Use MemoryEffects to represent intrinsic memory effects (NFCI) · feda983f
  Nikita Popov authored Nov 08, 2022
  feda983f
Nov 13, 2022
- [GlobalISel] Correct constant type in matchReassocConstantInnerLHS · 84822479
  chenglin.bi authored Nov 13, 2022
  84822479
Nov 11, 2022
- AtomicExpand: Support cmpxchg expansion for small FP types · 3cfa0385
  Matt Arsenault authored Sep 22, 2022
  3cfa0385
Nov 10, 2022
- [SelectDagISEL] refactor HandlePHINodesInSuccessorBlocks NFC. · f2981a3b
  Nick Desaulniers authored Nov 10, 2022
  f2981a3b
- [PEI][NFC] Refactoring of the debug instructions frame index replacement · 27091e62
  Alexander Timofeev authored Nov 09, 2022
  27091e62
- [SampleFDO] Persist profile staleness metrics into binary · 47b07580
  wlei authored Oct 25, 2022
  47b07580
Nov 08, 2022
- [TypePromotion] Replace Zext to Truncate for the case src bitwidth is larger · 597f4440
  chenglin.bi authored Nov 09, 2022
  597f4440
- Reland "[llvm][NFC] Use c++17 style variable type traits" · 6aa050a6
  Nathan James authored Nov 08, 2022
  6aa050a6
- Revert "[llvm][NFC] Use c++17 style variable type traits" · 632a389f
  Nathan James authored Nov 08, 2022
  632a389f
- [llvm][NFC] Use c++17 style variable type traits · 1834a310
  Nathan James authored Nov 08, 2022
  1834a310
- AMDGPU/GlobalISel: Fix combine crash because LI is not set in prelegalizer · 838d5d37
  Petar Avramovic authored Nov 08, 2022
  838d5d37
- [clang][pdb] Don't include -fmessage-length in PDB buildinfo · aa99b607
  Tobias Hieta authored Nov 08, 2022
  aa99b607
Nov 07, 2022
- [NFC][BlockPlacement]Add an option to renumber blocks based on function layout order. · 36e8e193
  Mingming Liu authored Nov 03, 2022
  36e8e193
- [SWP] Recognize mem carried dep with different base · c8be3529
  Thomas Preud'homme authored Oct 21, 2022
  c8be3529
- GlobalISel: Pass through AA metadata for target memory intrinsics · 162d9030
  Matt Arsenault authored Nov 05, 2022
  162d9030
Nov 05, 2022
- [NFC] Refactor DAGCombiner::foldSelectOfConstants to reduce nesting 2.0 · 82209fd9
  Amaury Séchet authored Nov 05, 2022
  
  82209fd9
- [NFC] Refactor DAGCombiner::foldSelectOfConstants to reduce nesting · 7c05f092
  Amaury Séchet authored Nov 05, 2022
  
  7c05f092
Nov 04, 2022
- [LLVM][AMDGPU] Specialize 32-bit atomic fadd instruction for generic address space · 1186e9d5
  Shilei Tian authored Nov 04, 2022
  1186e9d5
- [IR] Switch everything to use memory attribute · 304f1d59
  Nikita Popov authored Nov 02, 2022
  304f1d59
- [CodeGenPrep] Change ValueToSExts from DeseMap to MapVector · e419620f
  Haohai Wen authored Nov 04, 2022
  e419620f
Nov 03, 2022
- [StatepointLowering] remove unused parameter. NFC · 0589038a
  Nick Desaulniers authored Nov 03, 2022
  0589038a
- [SelectionDAGBuilder] use bitcast instead of AnyExtOrTrunc if copy parts from... · ef0d689e
  Henry Yu authored Nov 03, 2022
  ef0d689e
- [PowerPC] Add new DMR register classes to Future CPU. · 9df924a6
  Stefan Pintilie authored Nov 02, 2022
  9df924a6
- [GISel] Add (fsub +-0.0, X) -> fneg combine · 020a9d7b
  Pierre van Houtryve authored Oct 21, 2022
  020a9d7b
- WebAssembly: Move exception handling code together · cbce11c4
  Matt Arsenault authored Nov 02, 2022
  
  cbce11c4
- FunctionLoweringInfo: Use TLI member instead of finding it · 4fed59ed
  Matt Arsenault authored Nov 02, 2022
  
  4fed59ed
Nov 02, 2022
- [MIRVRegNamer] Avoid opcode hash collision · 2d8c1597
  John Brawn authored Oct 28, 2022
  2d8c1597
- [MachineCSE] Allow PRE of instructions that read physical registers · 88ac25b3
  John Brawn authored Oct 27, 2022
  88ac25b3
Nov 01, 2022
- [GlobalISel] Compute debug location when merging stores more accurately · 92ec6149
  Anton Sidorenko authored Oct 28, 2022
  92ec6149
- [VP][RISCV] Add vp.rint and RISC-V support. · 71e4e355
  Yeting Kuo authored Oct 24, 2022
  71e4e355
- AtomicExpand: Use InstSimplifyFolder · b60a9ccd
  Matt Arsenault authored Sep 20, 2022
  b60a9ccd
- AtomicExpand: Don't create unused instructions for some atomicrmw · 07f12170
  Matt Arsenault authored Sep 29, 2022
  07f12170
Oct 30, 2022
- [VectorUtils] Add getShuffleDemandedElts helper · 55a11b54
  Simon Pilgrim authored Oct 30, 2022
  55a11b54
Oct 29, 2022
- [DAG] Enable combineShiftOfShiftedLogic folds after type legalization · 78739fdb
  Simon Pilgrim authored Oct 29, 2022
  78739fdb
Oct 28, 2022
- [DAG] ExpandIntRes_MINMAX - simplify cases with sufficient number of sign bits · 69d117ed
  Simon Pilgrim authored Oct 28, 2022
  69d117ed