Commits · 07ed62b7d5514937a50b4af4feaa1969911d142e · Lorenzo Albano / LLVM bpEVL · GitLab

Mar 20, 2021
- [RISCV] Disable (mul (and X, 0xffffffff), (and Y, 0xffffffff)) optimization when Zba is enabled. · 07ed62b7
  Craig Topper authored Mar 20, 2021
  07ed62b7
- [RISCV] Add isel pattern to optimize (mul (and X, 0xffffffff), (and Y, 0xffffffff)) on RV64 · b0d8823a
  Craig Topper authored Mar 20, 2021
  b0d8823a
- [RISCV] Rename WriteShift/ReadShift scheduler classes to... · d5c1d305
  Craig Topper authored Mar 19, 2021
  d5c1d305
Mar 19, 2021
- [RISCV] Add missing bitcasts to the results of lowerINSERT_SUBVECTOR and... · 5d315691
  Craig Topper authored Mar 19, 2021
  5d315691
- [RISCV] Lower scalable vector masked loads to intrinsics to match fixed... · 85f3f6b3
  Craig Topper authored Mar 19, 2021
  85f3f6b3
- [RISCV] Maintain fixed-length info when optimizing BUILD_VECTORs · d399b82e
  Fraser Cormack authored Mar 19, 2021
  d399b82e
- [RISCV] Fix missing scalable->fixed-length vector conversion · 550292ec
  Fraser Cormack authored Mar 17, 2021
  550292ec
- [RISCV] Spilling for Zvlsseg registers. · aa8d33a6
  Hsiangkai Wang authored Mar 15, 2021
  aa8d33a6
- [RISCV] Correct the output chain in lowerFixedLengthVectorMaskedLoadToRVV · c9861f72
  Craig Topper authored Mar 18, 2021
  c9861f72
Mar 18, 2021
- [RISCV] Support scalable-vector masked scatter operations · 3495031a
  Fraser Cormack authored Feb 08, 2021
  3495031a
- [RISCV] Support scalable-vector masked gather operations · 0331399d
  Fraser Cormack authored Feb 04, 2021
  0331399d
- [RISCV] Support bitcasts of fixed-length mask vectors · c2b4600e
  Fraser Cormack authored Mar 17, 2021
  c2b4600e
- [RISCV] Fix isel pattern of masked vmslt[u] · fca5d63a
  ShihPo Hung authored Mar 17, 2021
  fca5d63a
Mar 17, 2021
- [RISCV] Use getTargetExtractSubreg and getTargetInsertSubreg to simplify some code. NFCI · 92b39c69
  Craig Topper authored Mar 17, 2021
  
  92b39c69
- [RISCV] Support masked load/store for fixed vectors. · 696ddef5
  Craig Topper authored Mar 17, 2021
  696ddef5
- [RISCV] Optimize "dominant element" BUILD_VECTORs · 70251759
  Fraser Cormack authored Mar 15, 2021
  70251759
Mar 16, 2021
- [RISCV] Support clang -fpatchable-function-entry && GNU function attribute... · 6ab89279
  Fangrui Song authored Mar 16, 2021
  6ab89279
- [RISCV] Look through copies when trying to find an implicit def in addVSetVL. · 229eeb18
  Craig Topper authored Mar 16, 2021
  229eeb18
- [RISCV] Improve i32 UADDSAT/USUBSAT on RV64. · a33ce06c
  Craig Topper authored Mar 16, 2021
  a33ce06c
Mar 15, 2021
- [RISCV] Add RISCVISD::BR_CC similar to RISCVISD::SELECT_CC. · 41759c3d
  Craig Topper authored Mar 15, 2021
  41759c3d
- [RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0) · 018e96f7
  Philipp Tomsich authored Mar 15, 2021
  018e96f7
- [RISCV] Improve legalization of i32 UADDO/USUBO on RV64. · 3dc5b533
  Craig Topper authored Mar 15, 2021
  3dc5b533
- [RISCV] Support fixed-length vectors in the calling convention · 0c5b789c
  Fraser Cormack authored Mar 02, 2021
  0c5b789c
- [RISCV] Support inline asm for vector instructions. · a81dff1e
  Hsiangkai Wang authored Mar 09, 2021
  a81dff1e
- [RISCV] Give an explicit error if 'generic' CPU is passed instead of... · fcdf7f62
  Craig Topper authored Mar 14, 2021
  fcdf7f62
Mar 13, 2021
- change rvv frame layout · a9b9c64f
  luxufan authored Feb 20, 2021
  a9b9c64f
Mar 12, 2021
- [RISCV] Teach normaliseSetCC to canonicalize X > -1 to X >= 0 and X < 1 to 0 >= X. · 51151828
  Craig Topper authored Mar 12, 2021
  51151828
- [RISCV] Add support for scalable vector masked load/store. · 45d3ed03
  Craig Topper authored Mar 12, 2021
  45d3ed03
- [RISCV] Optimize INSERT_VECTOR_ELT sequences · 641f5700
  Fraser Cormack authored Mar 08, 2021
  641f5700
- [RISCV] Fix up stale VECREDUCE comments. NFC. · 4d2d5855
  Fraser Cormack authored Mar 11, 2021
  4d2d5855
- [RISCV] Return false from isShuffleMaskLegal except for splats. · 1d26bbcf
  Craig Topper authored Mar 11, 2021
  1d26bbcf
Mar 11, 2021
- [RISCV] Support fixed vector copysign. · c82f4429
  Craig Topper authored Mar 11, 2021
  c82f4429
- [RISCV] Handle vmv.x.s intrinsic for i64 vectors on RV32. · 0dff8a96
  Craig Topper authored Mar 11, 2021
  0dff8a96
- [RISCV] Support extract_vector_elt for fixed and scalable masked registers. · 9c841cb8
  Craig Topper authored Mar 11, 2021
  9c841cb8
Mar 10, 2021
- [RISCV][SelectionDAG] Introduce an ISD::SPLAT_VECTOR_PARTS node that can... · 9106d045
  Craig Topper authored Mar 10, 2021
  9106d045
- [RISCV] Starting fixing issues that prevent us from testing vXi64 intrinsics on RV32. · 0c73a506
  Craig Topper authored Mar 10, 2021
  0c73a506
- [RISCV] Manually split vector operands to VECREDUCE when handling vXi64 vectors on RV32. · 1e391186
  Craig Topper authored Mar 10, 2021
  1e391186
Mar 09, 2021
- [RISCV] Add support for VECTOR_REVERSE for scalable vector types. · 351844ed
  Craig Topper authored Mar 09, 2021
  351844ed
- [RISCV] Add support for fixed vector reductions. · 77ac3166
  Craig Topper authored Mar 09, 2021
  77ac3166
- [RISCV] Don't modify the SEW immediate on the V extension pseudo instructions... · 1c7ad4dd
  Craig Topper authored Mar 09, 2021
  1c7ad4dd