- May 12, 2021
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Hana Joo authored
The `IgnoreArray` flag was not used before while running the rule. Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=47288 | b/47288 ]] Reviewed By: njames93 Differential Revision: https://reviews.llvm.org/D101239
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Tobias Gysi authored
after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612). Differential Revision: https://reviews.llvm.org/D102236
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Kristina Bessonova authored
Differential Revision: https://reviews.llvm.org/D102195
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Simon Pilgrim authored
Extend the HOP(HOP(X,Y),HOP(Z,W)) and SHUFFLE(HOP(X,Y),HOP(Z,W)) folds to handle repeating 256/512-bit vector cases. This allows us to drop the UNPACK(HOP(),HOP()) custom fold in combineTargetShuffle. This required isRepeatedTargetShuffleMask to be tweaked to support target shuffle masks taking more than 2 inputs.
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gbreynoo authored
The readelf command guide shows the short options used as aliases but these are not found in the help text unless --show-hidden is used, other tools show aliases with --help. This change fixes the help output to be consistent with the command guide. Differential Revision: https://reviews.llvm.org/D102173
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gbreynoo authored
In the help output of other tools and in the symbolizer command guide, Mach-O specific options are in their own section. This change fixes the symbolizer help output to be consistent. Differential Revision: https://reviews.llvm.org/D102178
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David Sherwood authored
In InnerLoopVectorizer::widenPHIInstruction there are cases where we have to scalarise a pointer induction variable after vectorisation. For scalable vectors we already deal with the case where the pointer induction variable is uniform, but we currently crash if not uniform. For fixed width vectors we calculate every lane of the scalarised pointer induction variable for a given VF, however this cannot work for scalable vectors. In this case I have added support for caching the whole vector value for each unrolled part so that we can always extract an arbitrary element. Additionally, we still continue to cache the known minimum number of lanes too in order to improve code quality by avoiding an extractelement operation. I have adapted an existing test `pointer_iv_mixed` from the file: Transforms/LoopVectorize/consecutive-ptr-uniforms.ll and added it here for scalable vectors instead: Transforms/LoopVectorize/AArch64/sve-widen-phi.ll Differential Revision: https://reviews.llvm.org/D101294
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Peter Waller authored
The sve.convert.to.svbool lowering has the effect of widening a logical <M x i1> vector representing lanes into a physical <16 x i1> vector representing bits in a predicate register. In general, if converting to svbool, the contents of lanes in the physical register might not be known. For sve.convert.to.svbool the new lanes are specified to be zeroed, requiring 'and' instructions to mask off the new lanes. For lanes coming from a ptrue or a comparison, however, they are known to be zero. CodeGen Before: ptrue p0.s, vl16 ptrue p1.s ptrue p2.b and p0.b, p2/z, p0.b, p1.b ret After: ptrue p0.s, vl16 ret Differential Revision: https://reviews.llvm.org/D101544
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Michał Górny authored
Add a function to read NT_PRPSINFO note from FreeBSD core dumps. This is necessary to get the process ID (NT_PRSTATUS has only thread ID). Move the lp64 check from NT_PRSTATUS parsing to the parseFreeBSDNotes() to avoid repeating it. Differential Revision: https://reviews.llvm.org/D101893
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Michał Górny authored
The FreeBSD coredumps from i386 systems contain only FSAVE-style NT_FPREGSET. Since we do not really support reading that kind of data anymore, just use NT_X86_XSTATE to get FXSAVE-style data when available. Differential Revision: https://reviews.llvm.org/D101086
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Stephen Tozer authored
Previous crashes caused by this patch were the result of machine subregisters being incorrectly handled in updateDbgUsersToReg; this has been fixed by using RegUnits to determine overlapping registers, instead of using the register values directly. Differential Revision: https://reviews.llvm.org/D101523 This reverts commit 7ca26c5f.
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Neal (nealsid) authored
I don't mean to undo others' work but it looks like the hand-rolled EditLine for LLDB on Windows isn't used. It'd be easier to make changes to bring the other platforms' Editline wrapper up to date (e.g. simplifying char vs wchar_t) without modifying/testing this one too. Reviewed By: amccarth Differential Revision: https://reviews.llvm.org/D102208
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Piotr Sobczak authored
No need to handle invariant loads when avoiding WAR conflicts, as there cannot be a vector store to the same memory location. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D101177
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Qiu Chaofan authored
This commit brought build break in some f128 related tests. But that's not the root cause. There exists some differences between Clang and GCC's definition for 128-bit float types on PPC, so macros/functions in glibc may not work with clang -mfloat128 well. We need to handle this carefully and reland it.
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Tomas Matheson authored
Based on the same for AArch64: 4751cadc At -O0, the fast register allocator may insert spills between the ldrex and strex instructions inserted by AtomicExpandPass when expanding atomicrmw instructions in LL/SC loops. To avoid this, expand to cmpxchg loops and therefore expand the cmpxchg pseudos after register allocation. Required a tweak to ARMExpandPseudo::ExpandCMP_SWAP to use the 4-byte encoding of UXT, since the pseudo instruction can be allocated a high register (R8-R15) which the 2-byte encoding doesn't support. However, the 4-byte encodings are not present for ARM v8-M Baseline. To enable this, two new pseudos are added for Thumb which are only valid for v8mbase, tCMP_SWAP_8 and tCMP_SWAP_16. The previously committed attempt in D101164 had to be reverted due to runtime failures in the test suites. Rather than spending time fixing that implementation (adding another implementation of atomic operations and more divergence between backends) I have chosen to follow the approach taken in D101163. Differential Revision: https://reviews.llvm.org/D101898 Depends on D101912
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Tomas Matheson authored
Differential Revision: https://reviews.llvm.org/D101912
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Alex Orlov authored
This fixes the following bugs: https://bugs.llvm.org/show_bug.cgi?id=43935 Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D102258
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Djordje Todorovic authored
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Guillaume Chatelet authored
This is a roll forward of D101895 with two additional fixes: Original Patch description: > This is a follow up on D101524 which: > > - simplifies cpu features detection and usage, > - flattens target dependent optimizations so it's obvious which implementations are generated, > - provides an implementation targeting the host (march/mtune=native) for the mem* functions, > - makes sure all implementations are unittested (provided the host can run them). Additional fixes: - Fix uninitialized ALL_CPU_FEATURES - Use non pseudo microarch as it is only supported from Clang 12 on Differential Revision: https://reviews.llvm.org/D102233
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Dmitry Vyukov authored
I was running: $ ninja check-sanitizer check-msan check-asan \ check-tsan check-lsan check-ubsan check-cfi \ check-profile check-memprof check-xray check-hwasan but missed check-scudo... Differential Revision: https://reviews.llvm.org/D102314
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Ulysse Beaugnon authored
DialectAsmParser already allows converting an llvm::SMLoc location to a mlir::Location location. This commit adds the same functionality to OpAsmParser. Implementation is copied from DialectAsmParser. Reviewed By: rriddle Differential Revision: https://reviews.llvm.org/D102165
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Dumitru Potop authored
First step in adding alignment as an attribute to MLIR global definitions. Alignment can be specified for global objects in LLVM IR. It can also be specified as a named attribute in the LLVMIR dialect of MLIR. However, this attribute has no standing and is discarded during translation from MLIR to LLVM IR. This patch does two things: First, it adds the attribute to the syntax of the llvm.mlir.global operation, and by doing this it also adds accessors and verifications. The syntax is "align=XX" (with XX being an integer), placed right after the value of the operation. Second, it allows transforming this operation to and from LLVM IR. It is checked whether the value is an integer power of 2. Reviewed By: ftynse, mehdi_amini Differential Revision: https://reviews.llvm.org/D101492
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Dmitry Vyukov authored
Add missing includes and use SYS_pipe2 instead of SYS_pipe as it's not present on some arches. Differential Revision: https://reviews.llvm.org/D102311
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Martin Storsjö authored
This matches how they are defined on X86. This should fix the relative lookup tables pass for COFF, allowing it to be reenabled. Differential Revision: https://reviews.llvm.org/D102217
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Dmitry Vyukov authored
We have some significant amount of duplication around CheckFailed functionality. Each sanitizer copy-pasted a chunk of code. Some got random improvements like dealing with recursive failures better. These improvements could benefit all sanitizers, but they don't. Deduplicate CheckFailed logic across sanitizers and let each sanitizer only print the current stack trace. I've tried to dedup stack printing as well, but this got me into cmake hell. So let's keep this part duplicated in each sanitizer for now. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102221
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Qiu Chaofan authored
Reviewed By: nemanjai, steven.zhang Differential Revision: https://reviews.llvm.org/D92815
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Kristina Bessonova authored
Split a few more debug mode tests missed in D100592. Differential Revision: https://reviews.llvm.org/D102194
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Dmitry Vyukov authored
setlocale interceptor imitates a write into result, which may be located in .rodata section. This is the only interceptor that tries to do this and I think the intention was to initialize the range for msan. So do that instead. Writing into .rodata shouldn't happen (without crashing later on the actual write) and this traps on my local tsan experiments. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102161
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Vitaly Buka authored
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Dmitry Vyukov authored
Currently we have: sanitizer_posix_libcdep.cpp:146:27: warning: cast between incompatible function types from ‘__sighandler_t’ {aka ‘void (*)(int)’} to ‘sa_sigaction_t’ 146 | sigact.sa_sigaction = (sa_sigaction_t)SIG_DFL; We don't set SA_SIGINFO, so we need to assign to sa_handler. And SIG_DFL is meant for sa_handler, so this gets rid of both compiler warning, type cast and potential runtime misbehavior. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102162
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Dmitry Vyukov authored
We already declare subset of annotations in test.h. But some are duplicated and declared in tests. Move all annotation declarations to test.h. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102152
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Qiu Chaofan authored
Vector single element update optimization is landed in 2db4979c. But the scope needs restriction. This patch restricts the index to inbounds and vector must be fixed sized. In future, we may use value tracking to relax constant restrictions. Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D102146
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Dmitry Vyukov authored
Add a test case reported in: https://github.com/google/sanitizers/issues/1401 and fix it. The code assumes sigwait will process other signals. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102057
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Dmitry Vyukov authored
Add a simple test that uses syscall annotations. Just to ensure at least basic functionality works. Also factor out annotated syscall wrappers into a separate header file as they may be useful for future tests. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102223
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Chia-hung Duan authored
Address the TODO of removing recursion while SSA naming. Reviewed By: mehdi_amini Differential Revision: https://reviews.llvm.org/D102226
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Vitaly Buka authored
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Congzhe Cao authored
This is a bugfix in the transformation phase. If the original outer loop header branches to both the inner loop (header) and the outer loop latch, and if there is an lcssa PHI node outside the loop nest, then after interchange the new outer latch will have an lcssa PHI node inserted which has two predecessors, i.e., the original outer header and the original outer latch. Currently the transformation assumes it has only one predecessor (the original outer latch) and crashes, since the inserted lcssa PHI node does not take both predecessors as incoming BBs. Reviewed By: Whitney Differential Revision: https://reviews.llvm.org/D100792
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Jim Ingham authored
Actually, I don't think this test is going to be stable enough to be worthwhile. Let me see if I can think of a better way to test this.
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Matt Arsenault authored
This was hardcoding the register class to use for the newly created pointer registers, violating the aligned VGPR requirement.
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Jim Ingham authored
The gdb-remote tests are a bit artificial, depending on Python threading, and sleeps. So I'm not 100% surprised it doesn't work straight up on another XSsystem.
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