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  1. Mar 12, 2019
  2. Mar 11, 2019
    • Sanjoy Das's avatar
      Revert "Relax constraints for reduction vectorization" · 2136a5bc
      Sanjoy Das authored
      This reverts commit r355868.  Breaks hexagon.
      
      llvm-svn: 355873
      2136a5bc
    • Craig Topper's avatar
      [X86] Remove ProcModel and ProcFeatures tablegen classes. Move all feature... · a958d40e
      Craig Topper authored
      [X86] Remove ProcModel and ProcFeatures tablegen classes. Move all feature lists into a ProcessorFeatures class.
      
      ProcFeatures was a class that just concatenated two feature lists together and gave it a name. We used it to inherit features between CPUs.
      
      ProcModel took a two CPU feature lists and concatenated them before deferring to ProcessorModel. This was to allow inherited features and specific features to be passed to each CPU.
      
      Both of these allowed for only very rigid CPU inheritance rules.
      
      With this patch we now store all of the lists we were using for inheritance in one object and do any list oncatenation we want there. Then we just pass whatever list we want from this class into the ProcessorModel class for each CPU.
      
      Hopefully this gives us more flexibility to build up feature lists in whatever ways we think make sense. Perhaps untangling ISA flags and tuning flags.
      
      I've only touched the CPUs that were directly affected by the removal of the ProcModel and ProcFeatures classes. We should move more of the feature lists into ProcessorFeatures.
      
      llvm-svn: 355872
      a958d40e
    • Jessica Paquette's avatar
      Recommit "[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT" · 607774c9
      Jessica Paquette authored
      After r355865, we should be able to safely select G_EXTRACT_VECTOR_ELT without
      running into any problematic intrinsics.
      
      Also add a fix for lane copies, which don't support index 0.
      
      llvm-svn: 355871
      607774c9
    • Evgeniy Stepanov's avatar
      Remove ASan asm instrumentation. · aedec3f6
      Evgeniy Stepanov authored
      Summary: It is incomplete and has no users AFAIK.
      
      Reviewers: pcc, vitalybuka
      
      Subscribers: srhines, kubamracek, mgorny, krytarowski, eraman, hiraditya, jdoerfert, #sanitizers, llvm-commits, thakis
      
      Tags: #sanitizers, #llvm
      
      Differential Revision: https://reviews.llvm.org/D59154
      
      llvm-svn: 355870
      aedec3f6
    • Alex Bradbury's avatar
      [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A · 4d20cc21
      Alex Bradbury authored
      AtomicCmpSwapWithSuccess is legalised into an AtomicCmpSwap plus a comparison.
      This requires an extension of the value which, by default, is a
      zero-extension. When we later lower AtomicCmpSwap into a PseudoCmpXchg32 and then expanded in
      RISCVExpandPseudoInsts.cpp, the lr.w instruction does a sign-extension.
      
      This mismatch of extensions causes the comparison to fail when the compared
      value is negative. This change overrides TargetLowering::getExtendForAtomicOps
      for RISC-V so it does a sign-extension instead.
      
      Differential Revision: https://reviews.llvm.org/D58829
      Patch by Ferran Pallarès Roca.
      
      llvm-svn: 355869
      4d20cc21
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