llvm-svn: 274574

    This reverts commit r259387 because it inserts illegal code after legalization
    in some backends where i64 OR type is illegal for example.

llvm-svn: 274573

Only support broadcast from vector register so far - memory folding support will have to wait.

llvm-svn: 274572

[X86][AVX512] Fixed decoding of permd/permpd variable mask shuffles + enabled them for target shuffle combining

Corrected element mask masking to extract the bottom index bits (now matches the perm2 implementation but for unary inputs).

llvm-svn: 274571

Not all code-paths set the relocation model to static for Windows.  This
currently breaks on Windows ARM with `-mlong-calls` when built with clang.
Loosen the assertion to what it was previously.  We would ideally ensure that
all the configuration sets Windows to static relocation model.

llvm-svn: 274570

This only really matters when the index is non-constant since the
constant case already gets taken care of by other combines.

llvm-svn: 274569

https://llvm.org/bugs/show_bug.cgi?id=28428

llvm-svn: 274568

The other use really does only care about the SDNode (it checks the
opcode against a whitelist), but bitFieldPlacement can be misled if
the node produces multiple results.

Patch by Ismail Badawi.

llvm-svn: 274567

The problem is that the parameter pack in a function type type alias is not
reexpanded after being transformed. Also remove an incorrect comment in a
similar function. Fixes PR26017.

Differential Revision: http://reviews.llvm.org/D21030

llvm-svn: 274566

This version should actually remove the empty directories I removed
all of the files from. Thanks to tstellar for pointing out git-svn's
--rmdir flag.

Original message:

This creates make/ninja targets like check-clang-codegen and
check-clang-unit, much like LLVM already has. I had to move some input
files into Input directories so they weren't picked up as test
directories.

llvm-svn: 274565

Because of the special immediate operand, the constant
bus is already used so SGPRs are never useful.

r263212 changed the name of the immediate operand, which
broke the verifier check for the restriction.

llvm-svn: 274564

llvm-svn: 274563

This reverts r274560. It's breaking a bunch of bots due to a directory
with a space in the name. Doesn't repro locally for some reason.

llvm-svn: 274562

Summary:
These have been replaced with TableGen code (except for isConstantLoad,
which is still used for R600).  The queries were broken for cases
where MemOperand was a PseudoSourceValue.

Reviewers: arsenm

Subscribers: arsenm, kzhuravl, llvm-commits

Differential Revision: http://reviews.llvm.org/D21684

llvm-svn: 274561

This creates make/ninja targets like check-clang-codegen and
check-clang-unit, much like LLVM already has. I had to move some input
files into Input directories so they weren't picked up as test
directories.

llvm-svn: 274560

Differential Revision: http://reviews.llvm.org/D21792

llvm-svn: 274559

This patch also removes the SCEV variants of getStepVector() since they have no
uses after the refactoring.

Differential Revision: http://reviews.llvm.org/D21903

llvm-svn: 274558

There is no need to specifically match for isl, but we can exclude anything in
lib/External from formatting as we assume that externally contributed code
should always match the upstream code. This simplifies the cmake script and
allows additional external projects to be added without the need to explicitly
exclude them from formatting.

llvm-svn: 274557

[AMDGPU] rename DS_1A1D_Off8_NORET to DS_1A2D_Off8_NORET as ds_write2xx use 2 source registers. NFC.

llvm-svn: 274556

llvm-svn: 274555

llvm-svn: 274554

Differential Revision: http://reviews.llvm.org/D21789

llvm-svn: 274553

Summary:

As changing virtual methods could break method overrides disable applying the fix and just warn.

Reviewers: alexfh, sbenza

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D21936

llvm-svn: 274552

Differential Revision: http://reviews.llvm.org/D21972

llvm-svn: 274551

llvm-svn: 274550

In the patch that introduced support for GCD barrier blocks, I removed releasing a group when leaving it (in dispatch_group_leave). However, this is necessary to synchronize leaving a group and a notification callback (dispatch_group_notify). Adding this back, simplifying dispatch_group_notify_f and adding a test case.

Differential Revision: http://reviews.llvm.org/D21927

llvm-svn: 274549

[tsan] dispatch_once interceptor will cause a crash/deadlock when the original dispatch_once is used

Because we use SCOPED_TSAN_INTERCEPTOR in the dispatch_once interceptor, the original dispatch_once can also be sometimes called (when ignores are enabled or when thr->is_inited is false). However the original dispatch_once function doesn’t expect to find “2” in the storage and it will spin forever (but we use “2” to indicate that the initialization is already done, so no waiting is necessary). This patch makes sure we never call the original dispatch_once.

Differential Revision: http://reviews.llvm.org/D21976

llvm-svn: 274548

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21986

llvm-svn: 274547

export_executable_symbols looks though the link libraries of the executable in
order to figure out transitive dependencies, but in doing so it assumes that
all link libraries are also targets. This is not true as of r273302, so adjust
it to check if they actually are targets.

llvm-svn: 274546

llvm-svn: 274545

llvm-svn: 274544

The important thing I was missing was ensuring newly added constants were kept in topological order. Repositioning the node is correct if the constant is newly added (so it has no topological ordering) but wrong if it already existed - positioning it next in the worklist would break the topological ordering.

Original commit message:
  [Thumb] Select a BIC instead of AND if the immediate can be encoded more optimally negated

  If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead;

    int i(int a) {
      return a & 0xfffffeec;
    }

  Used to produce:
      ldr r1, [CONSTPOOL]
      ands r0, r1
    CONSTPOOL: 0xfffffeec

  And now produces:
      movs    r1, #255
      adds    r1, #20  ; Less costly immediate generation
      bics    r0, r1

llvm-svn: 274543

add abs intrinsics that use native LLVM-IR.
change _mm512_mask[z]_and_epi{32|64} to use select intrinsic

Differential Revision: http://reviews.llvm.org/D21973

llvm-svn: 274542

Differential Revision: http://reviews.llvm.org/D21988

llvm-svn: 274541

- Added new Builtins: enqueue_kernel, get_kernel_work_group_size
and get_kernel_preferred_work_group_size_multiple.

These Builtins use custom check to diagnose parameters of the passed Blocks
i. e. variable number of 'local void*' type params, and check different
overloads specified in Table 6.31 of OpenCL v2.0.

- IR is generated as an internal library call for each OpenCL Builtin,
reusing ObjC Block implementation.

Review: http://reviews.llvm.org/D20249
llvm-svn: 274540

I deleted the extra mask parameter.

__m256i _mm256_permutexvar_epi64 (__m256i idx, __m256i a)
#include "immintrin.h"
Instruction: vpermq
CPUID Flags: AVX512VL + AVX512F
Description
Shuffle 64-bit integers in a across lanes using the corresponding index in idx, and store the results in dst.
Operation
FOR j := 0 to 3
  i := j*64
    id := idx[i+1:i]*64
      dst[i+63:i] := a[id+63:id]
      ENDFOR
      dst[MAX:256] := 0
      dst[MAX:256] := 0
      
(From: Intel intrinsics guide)        

llvm-svn: 274539

It turns out that MSVC requires this.

llvm-svn: 274538

llvm-svn: 274537

llvm-svn: 274536

This patch corresponds to review:
http://reviews.llvm.org/D20443

It changes the legalization strategy for illegal vector types from integer
promotion to widening. This only applies for vectors with elements of width
that is a multiple of a byte since we have hardware support for vectors with
1, 2, 3, 8 and 16 byte elements.
Integer promotion for vectors is quite expensive on PPC due to the sequence
of breaking apart the vector, extending the elements and reconstituting the
vector. Two of these operations are expensive.
This patch causes between minor and major improvements in performance on most
benchmarks. There are very few benchmarks whose performance regresses. These
regressions can be handled in a subsequent patch with a DAG combine (similar
to how this patch handles int -> fp conversions of illegal vector types).

llvm-svn: 274535