Commits · db85345f2d9f12ce79fa868603594130f2015352 · Roger Ferrer / llvm-epi · GitLab

Jun 20, 2022
- [BasicTTI] Allow generic handling of scalable vector fshr/fshl · db85345f
  Philip Reames authored Jun 20, 2022
  db85345f
- [llvm] Don't use Optional::hasValue (NFC) · e0e687a6
  Kazu Hirata authored Jun 20, 2022
  
  e0e687a6
- Revert "[GlobalOpt] Perform store->dominated load forwarding for stored once globals" · 13ff7d6f
  Arthur Eubanks authored Jun 20, 2022
  13ff7d6f
- Revert "[GlobalOpt] Preserve CFG analyses" · 1cd2c72b
  Arthur Eubanks authored Jun 20, 2022
  1cd2c72b
- [RISCV] Delete unexercised VL=0 vsetvli compatibility logic · 14847098
  Philip Reames authored Jun 20, 2022
  14847098
- [ConstantFolding] Respect denormal handling mode attributes when folding instructions · d3919a8c
  David Candler authored Jun 20, 2022
  d3919a8c
- [Alignment] Remove alignTo version taking a MaybeAlign · d3cf49e9
  Guillaume Chatelet authored Jun 20, 2022
  
  d3cf49e9
- [NFC] Simplify alignment code in MemorySanitizer · 589c8d6f
  Guillaume Chatelet authored Jun 20, 2022
  
  589c8d6f
- [NFC] Simplify alignment code in CoroFrame · 72968119
  Guillaume Chatelet authored Jun 20, 2022
  
  72968119
- [NFC] Simplify code · d154d0ac
  Guillaume Chatelet authored Jun 20, 2022
  
  d154d0ac
- [ConstraintElimination] Move logic to add constraint to helper (NFC). · cebe7ae8
  Florian Hahn authored Jun 20, 2022
  
  cebe7ae8
- [RISCV] Fold prepass back into InsertVSETVLI data flow [nfc-ish] · dc562d57
  Philip Reames authored Jun 20, 2022
  dc562d57
- [RISCV] Assert initial load/store SEW is the EEW · 820e84e0
  Philip Reames authored Jun 20, 2022
  820e84e0
- [ConstraintElimination] Move StackEntry up, to allow use earlier (NFC). · bd9632af
  Florian Hahn authored Jun 20, 2022
  
  bd9632af
- [AMDGPU] Reorder cases. NFC. · ba306216
  Jay Foad authored Jun 20, 2022
  
  ba306216
- [AArch64][SME] Add the zero intrinsic · 01335863
  David Sherwood authored Jun 14, 2022
  01335863
- [AMDGPU] Increase instruction cache line size to 128 bytes for GFX11 · d7762a3b
  Jay Foad authored Mar 10, 2021
  d7762a3b
- [AMDGPU] Remove a duplicate atomic fadd pattern · b8e32e80
  Jay Foad authored Jun 20, 2022
  b8e32e80
- [SystemZ] Remove unnecessary casts to SystemZInstrInfo (NFC). · 3432d40c
  Jonas Paulsson authored Jun 20, 2022
  3432d40c
- [SystemZ] Remove stray enum value in SystemZInstrInfo.h (NFC). · 4065ea8c
  Jonas Paulsson authored Jun 20, 2022
  4065ea8c
- [windows][support] Improve backtrace emitted in crash report without llvm-symbolizer · 7cd1c01c
  Ben Dunbobbin authored Jun 20, 2022
  7cd1c01c
- [AMDGPU][MC][GFX11] Correct disassembly of DPP variants of VOPC64 opcodes · 485e8b4f
  Dmitry Preobrazhensky authored Jun 20, 2022
  485e8b4f
- [LoopPeel] Forget SCEV for updated exit phi values. · cfc741bc
  Florian Hahn authored Jun 20, 2022
  cfc741bc
- [Alignment] Use 'previous()' method instead of scalar division · 03036061
  Guillaume Chatelet authored Jun 20, 2022
  03036061
- [AMDGPU][GlobalISel] Legalize G_FSUB for s16 · 6cae753b
  Mirko Brkusanin authored Jun 20, 2022
  6cae753b
- [ARM] Allow distributing postinc with PHI uses · 76f60931
  David Green authored Jun 20, 2022
  76f60931
- [NFC][Alignment] Remove max functions between Align and MaybeAlign · f1255186
  Guillaume Chatelet authored Jun 18, 2022
  f1255186
- [Alignment] Remove multiply by MaybeAlign · 009fe075
  Guillaume Chatelet authored Jun 20, 2022
  
  009fe075
- [SimplifyCFG] Try to merge edge block when threading (PR55765) · 2b089e9a
  Nikita Popov authored Jun 07, 2022
  2b089e9a
- [Coroutines] Only do symmetric transfer if optimization is on · 7782e080
  Chuanqi Xu authored Jun 20, 2022
  7782e080
- [DAG] Fold (srl (shl x, c1), c2) -> and(shl/srl(x, c3), m) · e4a124dd
  Simon Pilgrim authored Jun 20, 2022
  e4a124dd
- [AMDGPU] Limit GFX11 to using 128 VGPRs · 7050d5b9
  Jay Foad authored Feb 17, 2022
  7050d5b9
- [SelectionDAG] Enable WidenVecOp_VECREDUCE_SEQ for scalable vector · ab25e263
  Lian Wang authored Jun 14, 2022
  ab25e263
- [InstCombine] add vector support for (A >> C) == (B >> C) --> (A^B) u< (1 << C) · 0eff6c6b
  Chenbing Zheng authored Jun 20, 2022
  0eff6c6b
- [RISCV] Merge two similar asserts from different if/else blocks. NFC · 8780630d
  Craig Topper authored Jun 19, 2022
  
  8780630d
- [LoongArch] Add codegen support for part of conversion operations · cf71f97b
  Weining Lu authored Jun 20, 2022
  cf71f97b
- [LoongArch] Perform `and` combination with a shifted mask · 2ef7c4ce
  Weining Lu authored Jun 20, 2022
  2ef7c4ce
- [LoongArch] Add codegen support for the bitwise binary operations and part of other operations · 709e4ad0
  Weining Lu authored Jun 20, 2022
  709e4ad0
- [LoongArch] Add codegen support for fneg · efc70058
  Weining Lu authored Jun 20, 2022
  efc70058
- [LoongArch] Add codegen support for the binary operations · a9921155
  Weining Lu authored Jun 20, 2022
  a9921155