Commits · ea05ee90596ceaa361950f818980d4997e4437b9 · Roger Ferrer / llvm-epi · GitLab

Jan 28, 2022
- [RISCV] Preserve VL when truncating i64 gather/scatter indices on RV32. · ea05ee90
  Craig Topper authored Jan 28, 2022
  ea05ee90
- [RISCV] Use tablegen size for getInstSizeInBytes. · de0c2d75
  Craig Topper authored Jan 28, 2022
  de0c2d75
- [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 · a9d5bb92
  Kito Cheng authored Apr 06, 2021
  a9d5bb92
- [x86] try harder to scalarize a vector load with extracted integer op uses · b4b97ec8
  Sanjay Patel authored Jan 28, 2022
  b4b97ec8
- [RISCV][NFC] Make Zb* instruction naming match the convention used elsewhere in the RISC-V backend · 588f121a
  Alex Bradbury authored Jan 28, 2022
  588f121a
- [X86] SimplifyDemandedBitsForTargetNode - fold MOVMSK(YMM) -> MOVMSK(XMM) · c7bb3665
  Simon Pilgrim authored Jan 28, 2022
  c7bb3665
- [PowerPC] Update handling of splat loads for v4i32/v4f32/v2i64 to require non-extending loads. · 9cc5b064
  Amy Kwan authored Jan 27, 2022
  9cc5b064
- [AArch64][SVE][VLS] Move extends into arguments of comparisons · 81bd67e1
  David Truby authored Nov 16, 2021
  81bd67e1
- [X86] combineSetCCMOVMSK - don't fold MOVMSK(BITCAST(PCMPEQ(X,0))) ->... · 2a13beaa
  Simon Pilgrim authored Jan 28, 2022
  2a13beaa
- [SVE] Extend isel pattern coverage for BIC. · 49178a2c
  Paul Walker authored Jan 27, 2022
  49178a2c
- [X86] combineSetCCMOVMSK - match all_of patterns with X86ISD::CMP as well as X86ISD::SUB · cce6490e
  Simon Pilgrim authored Jan 28, 2022
  cce6490e
- [X86] Fix MOVMSK(CONCAT(X,Y)) -> MOVMSK(AND/OR(X,Y)) fold for float types and demanded elements · 93c9b39d
  Simon Pilgrim authored Jan 28, 2022
  93c9b39d
- [Sparc] Implement BFD_RELOC_NONE · a584b1a4
  Rainer Orth authored Jan 28, 2022
  a584b1a4
- [ARM] Don't look through pointer types in canTailPredicateLoop() · 93122b25
  Nikita Popov authored Jan 27, 2022
  93122b25
- [NVPTX] Remove fmin/fmax.NaN.f64 again · f7da4a5d
  Christian Sigg authored Jan 27, 2022
  f7da4a5d
- [WebAssembly] Nullify unnecessary setjmp invokes · 4f1244d7
  Heejin Ahn authored Jan 26, 2022
  4f1244d7
- [WebAssembly] Handle cleanuppad with no parent in Wasm SjLj · 20c1d9ce
  Heejin Ahn authored Jan 26, 2022
  20c1d9ce
- [WebAssembly] Error out for setjmp within catch clause for Wasm SjLj · 26d587cf
  Heejin Ahn authored Jan 26, 2022
  26d587cf
- [WebAssembly] Don't copy noreturn attr to invokes · 786da406
  Heejin Ahn authored Jan 25, 2022
  786da406
- [WebAssembly] Treat __cxa_end_catch not longjmpable in Emscripten SjLj · d9517efb
  Heejin Ahn authored Jan 21, 2022
  d9517efb
- [RISCV] Add support for matching vwmulsu from fixed vectors · 6d6c44a3
  Chenbing.Zheng authored Jan 28, 2022
  6d6c44a3
Jan 27, 2022
- [SystemZ] Don't shrink 64-bit FP constants. · 9ca9fee6
  Jonas Paulsson authored Jan 21, 2022
  9ca9fee6
- [SystemZ] Implement orderFrameObjects(). · f541a504
  Jonas Paulsson authored Jan 21, 2022
  f541a504
- [RISCV] Prefer vmslt.vx v0, v8, zero over vmsle.vi v0, v8, -1. · 70e1cc67
  Craig Topper authored Jan 27, 2022
  70e1cc67
- [ARM][AArch64] Introduce qrdmlah and qrdmlsh intrinsics · 82973edf
  David Green authored Jan 27, 2022
  82973edf
- [X86] Fold MOVMSK(CONCAT(X,Y)) -> MOVMSK(AND/OR(X,Y)) for all_of/any_of patterns · 9103b73f
  Simon Pilgrim authored Jan 27, 2022
  9103b73f
- [AMDGPU] SILoadStoreOptimizer: reject AGPR DS_WRITE sooner · 4b133cee
  Jay Foad authored Jan 27, 2022
  4b133cee
- [AMDGPU] SILoadStoreOptimizer: use separate lists for AGPR instructions · 94a4594c
  Jay Foad authored Jan 27, 2022
  94a4594c
- [AMDGPU] SILoadStoreOptimizer: tweak API of CombineInfo::setMI. NFC. · 8a52fef1
  Jay Foad authored Jan 27, 2022
  8a52fef1
- AMDGPU: Handle addrspacecast of constant 32-bit to flat · 33b45ee4
  Matt Arsenault authored Jan 26, 2022
  33b45ee4
- [AArch64][SVE] Folds VSELECT if the predicate is all active. · af1c8f0d
  Sander de Smalen authored Jan 27, 2022
  af1c8f0d
- AMDGPU/GlobalISel: Fix assert on invalid cond code for llvm.amdgcn.icmp · aa88b653
  Matt Arsenault authored Jan 18, 2022
  
  aa88b653
- AMDGPU/GlobalISel: Fix flat_scratch_init handling for shaders · f482e869
  Matt Arsenault authored Jan 18, 2022
  f482e869
- [X86][SSE] Add combineBitOpWithShift for BITOP(SHIFT(X,Z),SHIFT(Y,Z)) ->... · ccda0f22
  Simon Pilgrim authored Jan 27, 2022
  ccda0f22
- [AMDGPU] SILoadStoreOptimizer: Allow merging across a swizzled access · 185cb8e8
  Jay Foad authored Jan 26, 2022
  185cb8e8
- [X86] Fold TESTZ(OR(LO(X),HI(X)),OR(LO(Y),HI(Y))) -> TESTZ(X,Y) · 389ae775
  Simon Pilgrim authored Jan 27, 2022
  389ae775
- [AArch64][SVE] Avoid using ptrue for unpredicated predicate AND. · dafd1f29
  Sander de Smalen authored Jan 27, 2022
  dafd1f29
- [AArch64][SVE] Avoid using ptrue for ptest in VECREDUCE_OR. · 417a75c6
  Sander de Smalen authored Jan 27, 2022
  417a75c6
- [AArch64][SVE] Implement missing lowering for extract_subvector for predicates. · c9da81d9
  Sander de Smalen authored Jan 27, 2022
  c9da81d9
- [AArch64][SVE] Implement PFALSE with explicit AArch64ISD node. · d58757e5
  Sander de Smalen authored Jan 27, 2022
  d58757e5