Commits · ee8aa351e43f27e1dd4240560a3e054ca045186f · Roger Ferrer / llvm-epi · GitLab

Apr 28, 2022
- [X86] Check the address in machine verifier · 6a6b0e4a
  Shengchen Kan authored Apr 26, 2022
  6a6b0e4a
Apr 22, 2022
- MIR: Serialize FunctionContextIdx in MachineFrameInfo · 9c122537
  Matt Arsenault authored Apr 21, 2022
  
  9c122537
Apr 20, 2022
- AMDGPU: Serialize VGPRForAGPRCopy · 987df725
  Matt Arsenault authored Apr 16, 2022
  
  987df725
- AMDGPU: Fix allocating GDS globals to LDS offsets · b5ec1312
  Matt Arsenault authored Apr 16, 2022
  b5ec1312
- AMDGPU: Serialize a few more MachineFunctionInfo fields in MIR · 378bb801
  Matt Arsenault authored Apr 16, 2022
  
  378bb801
- AMDGPU: Serialize gds size in MIR · f90f4884
  Matt Arsenault authored Apr 16, 2022
  
  f90f4884
- AMDGPU: Serialize WWM registers · 5cd17f9d
  Matt Arsenault authored Apr 16, 2022
  
  5cd17f9d
Apr 16, 2022
- MIR: Serialize a few bool function fields · b8033de0
  Matt Arsenault authored Apr 14, 2022
  
  b8033de0
Apr 12, 2022
- GlobalISel: Verify atomic load/store ordering restriction · 5a5034d5
  Matt Arsenault authored Apr 10, 2022
  5a5034d5
- AArch64/GlobalISel: Regenerate mir test checks · 7e8ff962
  Matt Arsenault authored Apr 09, 2022
  7e8ff962
Apr 08, 2022
- [RISCV][NFC] Add missing lit.local.cfg in test/CodeGen/MIR/RISCV/ · 5286c7ae
  Kito Cheng authored Apr 08, 2022
  
  5286c7ae
- [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file · 690085c9
  Kito Cheng authored Apr 06, 2022
  690085c9
Apr 06, 2022
- MIRParser: Fix asserting with invalid flags on machine operands · ced1250b
  Matt Arsenault authored Mar 28, 2022
  ced1250b
Mar 09, 2022
- [AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range · 04fff547
  Venkata Ramanaiah Nalamothu authored Mar 08, 2022
  04fff547
Feb 24, 2022
- [MIRParser] Diagnose too large align values in MachineMemOperands · 719bac55
  Jay Foad authored Feb 23, 2022
  719bac55
Feb 21, 2022
- MIR: Start diagnosing too many operands on an instruction · 9c7ca51b
  Matt Arsenault authored Feb 18, 2022
  9c7ca51b
Feb 02, 2022
- [AMDGPU] Use new target MMO flag MONoClobber · ddd3807e
  Jay Foad authored Feb 02, 2022
  ddd3807e
Dec 22, 2021
- Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" · 09b53296
  Ron Lieberman authored Dec 22, 2021
  09b53296
- [AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range · 9075009d
  RamNalamothu authored Dec 22, 2021
  9075009d
Dec 04, 2021
- AMDGPU: Enable fixed function ABI by default · 729bf9b2
  Matt Arsenault authored Aug 14, 2021
  729bf9b2
Nov 29, 2021
- [DebugInfo][InstrRef][NFC] "Final" x86 test cleanup · fc9dae42
  Jeremy Morse authored Nov 29, 2021
  fc9dae42
Nov 17, 2021
- [DebugInfo][NFC] Force some tests to not use instruction-referencing · 1dc0e47c
  Jeremy Morse authored Nov 17, 2021
  1dc0e47c
Nov 07, 2021
- [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC · d391e4fe
  Simon Pilgrim authored Nov 07, 2021
  d391e4fe
Oct 07, 2021
- DebugInfo: Use clang's preferred names for integer types · f6a561c4
  David Blaikie authored Sep 24, 2021
  f6a561c4
Oct 06, 2021
- Reland [IR] Increase max alignment to 4GB · 05392466
  Arthur Eubanks authored Sep 24, 2021
  05392466
- Revert "Reland [IR] Increase max alignment to 4GB" · 569346f2
  Arthur Eubanks authored Oct 06, 2021
  569346f2
- Reland [IR] Increase max alignment to 4GB · 8d64314f
  Arthur Eubanks authored Sep 24, 2021
  8d64314f
- Revert "[IR] Increase max alignment to 4GB" · 72cf8b60
  Arthur Eubanks authored Oct 06, 2021
  72cf8b60
- [IR] Increase max alignment to 4GB · df84c1fe
  Arthur Eubanks authored Sep 24, 2021
  df84c1fe
Sep 18, 2021
- [Tests] Fix incorrect noalias metadata · 80110aaf
  Nikita Popov authored Sep 16, 2021
  80110aaf
Sep 10, 2021
- AMDGPU: Invert ABI attribute handling · 722b8e0e
  Matt Arsenault authored Aug 14, 2021
  722b8e0e
Aug 26, 2021
- The maximal representable alignment in LLVM IR is 1GiB, not 512MiB · 564d85e0
  Roman Lebedev authored Aug 26, 2021
  564d85e0
Aug 10, 2021
- [X86] AVX512FP16 instructions enabling 1/6 · 6f7f5b54
  Wang, Pengfei authored Aug 10, 2021
  6f7f5b54
Jun 30, 2021
- CodeGen: Print/parse LLTs in MachineMemOperands · fae05692
  Matt Arsenault authored May 19, 2021
  fae05692
Jun 29, 2021
- [MIRParser] Add machine metadata. · e818efac
  Michael Liao authored May 25, 2021
  e818efac
Jun 14, 2021
- Implement DW_CFA_LLVM_* for Heterogeneous Debugging · 167e7afc
  RamNalamothu authored Jun 14, 2021
  167e7afc
Jun 07, 2021
- AMDGPU: Move codegen test out of MIR test directory · ccf28ea8
  Matt Arsenault authored Jun 05, 2021
  ccf28ea8
May 25, 2021
- [AMDGPU] Lower kernel LDS into a sorted structure · 8de4db69
  Stanislav Mekhanoshin authored May 19, 2021
  8de4db69
May 24, 2021
- Revert "[NFC] remove explicit default value for strboolattr attribute in tests" · 4ab3041a
  serge-sans-paille authored May 24, 2021
  4ab3041a
- [NFC] remove explicit default value for strboolattr attribute in tests · bda6e5be
  serge-sans-paille authored May 23, 2021
  bda6e5be