Commits · eff53ce8fc06b2379114955d5a2f77c24f483d1a · Roger Ferrer / llvm-epi · GitLab

Jul 31, 2023
- [RISCV] Remove unused CHECK prefix from test. NFC · eff53ce8
  Craig Topper authored Jul 30, 2023
  
  eff53ce8
- [RISCV] Use x0 in vsetvli when avl is equal to vlmax. · b7408ebb
  Jianjian GUAN authored Jul 27, 2023
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Jul 28, 2023
- [RISCV] A test for conditional binary ops. · cb15e657
  Mikhail Gudim authored Jul 17, 2023
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- [RISCV] Add support for XCVbi extension in CV32E40P · afb9c04a
  melonedo authored Jul 28, 2023
  afb9c04a
- Revert "[RISCV] Add support for XCVbi extension in CV32E40P" · e4777dc4
  melonedo authored Jul 28, 2023
  e4777dc4
- Revert "[RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF" · d5f496a2
  Kevin Athey authored Jul 28, 2023
  d5f496a2
- [RISCV] Add support for XCVbi extension in CV32E40P · bf2ad26b
  melonedo authored Jun 25, 2023
  bf2ad26b
- [RISCV] Add support for XCVsimd extension in CV32E40P · 3c0604b2
  melonedo authored Jun 11, 2023
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- [RISCV] Remove some instructions from Zvfbfwma by implying Zfbfmin according to the latest spec · e56bf133
  Jun Sha (Joshua) authored Jul 28, 2023
  e56bf133
- [RISCV] Add support for XCValu extension in CV32E40P · 092e60a3
  Qihan Cai authored Jul 20, 2023
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- [RISCV] Add codegen support for bf16 vector · 2b6df4a3
  Jun Sha (Joshua) authored Jul 28, 2023
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- [RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF · 9cf67592
  Philip Reames authored Jul 27, 2023
  9cf67592
Jul 27, 2023
- [RISCV] When using vror.vi for left rotate, mask the inverted immediate to SEW. · a81e1f0f
  Craig Topper authored Jul 27, 2023
  a81e1f0f
- [RISCV][GlobalISel] Test legalization of binary logical instructions with wider types · 474cf4fe
  Nitin John Raj authored Jul 26, 2023
  474cf4fe
Jul 26, 2023
- [RISCV] Add SDNode patterns for vwsll.[vv,vx,vi] · 33a93a41
  Luke Lau authored Jul 20, 2023
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- [RISCV] Add patterns for vnsrl.vx where shift amount is truncated · ce8f094d
  Luke Lau authored Jul 20, 2023
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- [RISCV] Add tests for vnsrl.vx where shift amount is truncated · 7c652feb
  Luke Lau authored Jul 20, 2023
  7c652feb
- [RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel. · e28307e9
  Craig Topper authored Jul 26, 2023
  e28307e9
- [FPEnv][RISC-V] Correct a strictfp test. · 5ad2760a
  Kevin P. Neal authored Jul 25, 2023
  5ad2760a
- [RISCV] Merge rv32/rv64 vector slideup and slidedown intrinsic tests that have... · 2f726c22
  Jim Lin authored Jul 26, 2023
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Jul 25, 2023
- [RISCV] Add DAG combine to pull xor with 1 through select idiom that uses czero_eqz/nez. · f6dc75cd
  Craig Topper authored Jul 25, 2023
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- [RISCV] Generalize combineAddOfBooleanXor to support any boolean not just setcc. · b34a8b3a
  Craig Topper authored Jul 25, 2023
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- [RISCV] Add simple DAG combine to pull xor with 1 through select_cc. · 5ff5dac8
  Craig Topper authored Jul 25, 2023
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- [RISCV] Merge rv32/rv64 vector narrowing integer right shift intrinsic tests... · 4eff7fae
  Jim Lin authored Jul 25, 2023
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- [RISCV] Match ext_vl+sra_vl/srl_vl+trunc_vector_vl to vnsra.wv/vnsrl.wv · 620e61c5
  LiaoChunyu authored Jul 25, 2023
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Jul 24, 2023
- [RISCV] Add lowering for scalar fmaximum/fminimum. · 49429783
  Craig Topper authored Jul 24, 2023
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- [RISCV] Adjust memcpy lowering test coverage w/V · a6cd1f62
  Philip Reames authored Jul 24, 2023
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- [RISCV] Add memcpy lowering test coverage with and without V · 4f4f4913
  Philip Reames authored Jul 24, 2023
  
  4f4f4913
- [RISCV] Add CZERO_EQZ/CZERO_NEZ to ComputeNumSignBitsForTargetNode. · 5990199e
  Craig Topper authored Jul 24, 2023
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- [RISCV] Add test case for D156082 to condops.ll · 82686d7d
  Craig Topper authored Jul 24, 2023
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- [RISCV] Add CZERO_EQZ/CZERO_NEZ to computeKnownBitsForTargetNode. · 9da0db4d
  Craig Topper authored Jul 24, 2023
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- [RISCV] Set Fast flag for unaligned memory accesses · 5b95bba6
  Luke Lau authored Jul 24, 2023
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- [DAGCombine] Canonicalize operands for visitANDLike · 595d5f36
  WANG Rui authored Jul 24, 2023
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- [RISCV] Add tests for (and (add x, c1), (lshr y, c2)) · cea980f3
  WANG Rui authored Jul 24, 2023
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- [RISCV] Add Zicond RUN lines to xaluo.ll. NFC · 74d16b21
  Craig Topper authored Jul 23, 2023
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- [RISCV] Remove unused check prefixes for tests. NFC · 37b474a2
  Jim Lin authored Jul 24, 2023
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- [RISCV] Support register allocation for GHC when f/d is not specified in the architecture · 78d91df4
  eopXD authored Jul 20, 2023
  78d91df4
- [RISCV] Add codegen for Zfbfmin instructions · f375ee36
  Jun Sha (Joshua) authored Jul 24, 2023
  f375ee36
Jul 22, 2023
- Revert "[RISCV] Add test which shows alignment of constant pools and the functions which followed" · 785939c1
  Philip Reames authored Jul 21, 2023
  785939c1
- [RISCV] Add test which shows alignment of constant pools and the functions which followed · cbf2a6ce
  Philip Reames authored Jul 21, 2023
  
  cbf2a6ce