Commits · f2b4b2ebe7a3c1d85a138fc729faf5c3ccb2e941 · Roger Ferrer / llvm-epi · GitLab

Dec 10, 2021
- [AArch64][GlobalISel] Split vector stores of zero. · 98095afb
  Amara Emerson authored Dec 09, 2021
  98095afb
Oct 02, 2021
- [AArch64][GlobalISel] Change G_ANYEXT fed by scalar G_ICMP to G_ZEXT · 96843d22
  Jessica Paquette authored Oct 01, 2021
  96843d22
Sep 29, 2021
- [AArch64][GlobalISel] Run overlapping_and after legalization · 241c7b14
  Jessica Paquette authored Sep 28, 2021
  241c7b14
Aug 11, 2021
- [AArch64][GlobalISel] Add ptradd_immed_chain combine to post-legalizer combiner. · 2c1789bc
  Amara Emerson authored Aug 11, 2021
  
  2c1789bc
Jul 27, 2021
- [AArch64][GlobalISel] Add identity combines to post-legal combiner. · 172051a1
  Amara Emerson authored Jul 26, 2021
  172051a1
Jul 26, 2021
- [GlobalISel] Add a constant folding combine. · c658b472
  Amara Emerson authored Jul 25, 2021
  c658b472
- [AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT. · 6af8d360
  Amara Emerson authored Jul 25, 2021
  6af8d360
- [AArch64][GlobalISel] Enable some select combines after legalization. · 0d41d219
  Amara Emerson authored Jul 25, 2021
  0d41d219
- [GlobalISel] Add combine for merge(unmerge) and use AArch64 postlegal-combiner. · dec34104
  Amara Emerson authored Jul 24, 2021
  dec34104
Jun 28, 2021
- [AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX · f9f5d415
  Brendon Cahoon authored Apr 30, 2021
  f9f5d415
Jun 01, 2021
- [GlobalISel][AArch64] Combine and (lshr x, cst), mask -> ubfx x, cst, width · e7f501b5
  Jessica Paquette authored Mar 24, 2021
  e7f501b5
May 19, 2021
- Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" · 84ae1cf8
  Jessica Paquette authored May 19, 2021
  84ae1cf8
- Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" · 52a77976
  Nico Weber authored May 19, 2021
  52a77976
May 18, 2021
- [GlobalISel] Simplify G_ICMP to true/false when the result is known · 892497c8
  Jessica Paquette authored May 14, 2021
  892497c8
May 11, 2021
- [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. · ae2b36e8
  Amara Emerson authored Jan 24, 2021
  ae2b36e8
- [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps · 79be9c59
  Jessica Paquette authored May 03, 2021
  79be9c59
May 08, 2021
- [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0. · 5b158093
  Amara Emerson authored May 06, 2021
  5b158093
Apr 29, 2021
- [AArch64][GlobalISel] Simplify out of range rotate amount. · 96ec6d91
  Amara Emerson authored Apr 26, 2021
  96ec6d91
Apr 10, 2021
- [AArch64][GlobalISel] Swap compare operands when it may be profitable · 49c3565b
  Jessica Paquette authored Nov 09, 2020
  49c3565b
Mar 30, 2021
- [GlobalISel][AArch64] Combine G_SEXT_INREG + right shift -> G_SBFX · 70043112
  Jessica Paquette authored Mar 23, 2021
  70043112
Mar 19, 2021
- Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" · 0ca83730
  Jessica Paquette authored Mar 18, 2021
  0ca83730
Mar 08, 2021
- [AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP · 5c26be21
  Jessica Paquette authored Mar 01, 2021
  5c26be21
Feb 23, 2021
- Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt" · ef1f7f1d
  Jessica Paquette authored Feb 23, 2021
  ef1f7f1d
- Revert "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt" · 662402a8
  Jessica Paquette authored Feb 22, 2021
  662402a8
Feb 22, 2021
- [AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt · 867e379c
  Jessica Paquette authored Feb 19, 2021
  867e379c
Feb 19, 2021
- [AArch64][GlobalISel] Run redundant_sext_inreg in the post-legalizer combiner · 8d3442ed
  Jessica Paquette authored Feb 17, 2021
  8d3442ed
Feb 16, 2021
- Revert "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" · 962b73dd
  Jessica Paquette authored Feb 16, 2021
  962b73dd
Feb 12, 2021
- [AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE · 61b4702a
  Jessica Paquette authored Feb 11, 2021
  61b4702a
Jan 29, 2021
- [AArch64][GlobalISel] Add a combine to fold away truncate in: G_ICMP EQ/NE (G_TRUNC(v), 0) · be62b3ba
  Amara Emerson authored Jan 26, 2021
  be62b3ba
Nov 11, 2020
- [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG. · 22623930
  Amara Emerson authored Nov 09, 2020
  22623930
Nov 10, 2020
- [GlobalISel] Add combine for (x | mask) -> x when (x | mask) == x · a75d6178
  Mirko Brkusanin authored Nov 06, 2020
  a75d6178
- [GlobalISel] Expand combine for (x & mask) -> x when (x & mask) == x · fb36ab0a
  Mirko Brkusanin authored Nov 06, 2020
  fb36ab0a
Nov 05, 2020
- [AArch64][GlobalISel] Add AArch64::G_DUPLANE[X] opcodes for lane duplicates. · f347d78c
  Amara Emerson authored Nov 04, 2020
  f347d78c
Nov 04, 2020
- [AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD. · 393b5538
  Amara Emerson authored Nov 03, 2020
  393b5538
Oct 23, 2020
- [AArch64][GlobalISel] Move imm adjustment for G_ICMP to post-legalizer lowering · 19dc9c97
  Jessica Paquette authored Oct 20, 2020
  19dc9c97
Oct 22, 2020
- [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0 · 147b9497
  Jessica Paquette authored Oct 19, 2020
  147b9497
Sep 28, 2020
- [GlobalISel] Combine (xor (and x, y), y) -> (and (not x), y) · a52e7801
  Jessica Paquette authored Sep 18, 2020
  a52e7801
Sep 22, 2020
- [AArch64][GlobalISel] Add a post-legalize combine for lowering vector-immediate G_ASHR/G_LSHR. · a513fdec
  Amara Emerson authored Sep 21, 2020
  a513fdec
Sep 09, 2020
- [GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less. · cc76da7a
  Amara Emerson authored Aug 24, 2020
  cc76da7a
Aug 19, 2020
- [GlobalISel] Add combine for (x & mask) -> x when (x & mask) == x · d25b12bd
  Jessica Paquette authored Aug 06, 2020
  d25b12bd