llvm-svn: 228146

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7376

llvm-svn: 228145

While probably technically correct, the solution r228138 was quite hard
to read/understand. This should be simpler.

Also added a test to ensure that we are still visiting the syntactic form
as well.

llvm-svn: 228144

Summary:
Named registers with the constraint "=&r" currently lose the early clobber flag
and turn into "=r" when converted to LLVM-IR. This patch correctly passes it on.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D7346

llvm-svn: 228143

llvm-svn: 228142

A previous commit added Cortex-A72 to LLVM, this teaches Clang to
accept it as well.

Patch by Ranjeet Singh.

llvm-svn: 228141

Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp
load balancing pass isn't enabled for Cortex-A72 as it's not
profitable to have it enabled for this core.

Patch by Ranjeet Singh.

llvm-svn: 228140

llvm-svn: 228139

Otherwise, this can lead to unexpected results when AST matching as
some nodes are only present in the semantic form.

For example, only looking at the syntactic form does not find the
DeclRefExpr to f() in:

  struct S { S(void (*a)()); };
  void f();
  S s[1] = {&f};

llvm-svn: 228138

to fix the interface_symbols_darwin.c test.

llvm-svn: 228137

llvm-svn: 228136

This associates movss and movsd with the packed single and packed double
execution domains (resp.). While this is largely cosmetic, as we now
don't have weird ping-pong-ing between single and double precision, it
is also useful because it avoids the domain fixing algorithm from seeing
domain breaks that don't actually exist. It will also be much more
important if we have an execution domain default other than packed
single, as that would cause us to mix movss and movsd with integer
vector code on a regular basis, a very bad mixture.

llvm-svn: 228135

Summary: This reduces the bloat in the source tree and makes the tests more consistent.

Reviewers: vharron, zturner

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D7373

llvm-svn: 228134

a register. We have lots of tests covering this.

llvm-svn: 228133

version of the script.

Changes include:
- Using the VEX prefix
- Skipping more detail when we have useful shuffle comments to match
- Matching more shuffle comments that have been added to the printer
  (yay!)
- Matching the destination registers of some AVX instructions
- Stripping trailing whitespace that crept in
- Fixing indentation issues

Nothing interesting going on here. I'm just trying really hard to ensure
these changes don't show up in the diffs with actual changes to the
backend.

llvm-svn: 228132

This is done in a bit of a strange way to use a multiline RE instead of
looping over the lines. Suggestions welcome here for a more pythonic way
of doing this as long as its reasonably fast.

llvm-svn: 228131

Summary:
Both LLDB and LLGS are leaking file descriptors into the debugged process. This plugs the leak by
closing the unneeded descriptors. In one case I use O_CLOEXEC, which I hope is supported on
relevant platforms. I also added a regression test and plugged a fd leak in dosep.py.

Reviewers: vharron, clayborg

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D7372

llvm-svn: 228130

This reverts patches 223862, 224198, 224203, and 224754, which were all
related to the vector load/store combining and were reverted/reaplied
a few times due to the same alignment problems we're seeing now.

Further tests, mainly self-hosting Clang, will be needed to reapply this
patch in the future.

llvm-svn: 228129

lldb-mi has 3 threads.
1. One that waits for user intput.
2. Another waits for 1st thread to get input command.
3. Waits for events from lldb.

2 & 3 needs to be synchronized so that they don't end up
doing things at same time. For example, while "break insert" is
processing, we can get a breakpoint event. Depending on where we
are in "break-insert", it can have different behavior. In some
cases, it can cause breakpoint to be deleted too. I have added a 
mutex so that command processing and event processing are done 
exclusively and they are not running at the same time.

In longer term, I think thread 2 & 3 should be merged to be only 
one thread which can wait on command or events.

Reviewed in http://reviews.llvm.org/D7371.

llvm-svn: 228128

instructions.

No actual change here.

llvm-svn: 228127

zero for v8i16 as well.

These exhibit the same domain badness, but also exhibit other weaknesses
in our blend lowering. More fixes to come.

llvm-svn: 228126

Differential Revision: http://reviews.llvm.org/D7342

llvm-svn: 228125

This is the simplest form of bit-math based blending which only fires
when we are blending with zero and is relatively profitable. I've only
enabled this path on very specific lowering strategies. I'm planning to
widen its applicability in subsequent patches, but so far you'll notice
that even though we get fewer shufps instructions, we *still* do the bit
math in the FP execution port. I'm looking into why this is still
happening.

llvm-svn: 228124

Specifically, the existing patterns were scalar-only. These cover the
packed vector bitwise operations when specifically requested with pseudo
instructions. This is particularly important in SSE1 where we can't
actually emit a logical operation on a v2i64 as that isn't a legal type.

This will be tested in subsequent patches which form the floating point
and patterns in more places.

llvm-svn: 228123

llvm-svn: 228122

llvm-svn: 228121

__declspec(restrict) and __attribute(malloc) are both handled
identically by clang: they are allowed to the noalias LLVM attribute.

Seeing as how noalias models the C99 notion of 'restrict', rename the
internal clang attribute to Restrict from Malloc.

llvm-svn: 228120

Fixes a regression introduced in r209149.

llvm-svn: 228119

When the condition is a vector, OpenCL specifies additional
requirements on the operand types, and also the operations
required to determine the result type of the operator. This is a
combination of OpenCL v1.1 s6.3.i and s6.11.6, and the semantics
remain unchanged in later versions of OpenCL.

llvm-svn: 228118

llvm-svn: 228117

llvm-svn: 228116

Removed trailing whitespace.

From: Vince Harron <vharron@google.com>
llvm-svn: 228115

llvm-svn: 228114

Some standard header files from MSVC2012 use 'mutable' on references, though it is directly prohibited by the standard.
Fix for http://llvm.org/PR22444
Differential Revision: http://reviews.llvm.org/D7370

llvm-svn: 228113

llvm-svn: 228112

llvm-svn: 228111

llvm-svn: 228110

The ARM assembler allows register alias redefinitions as long as it
targets the same register. r222319 broke that. In the AArch64 case
it would just produce a new warning, but in the ARM case it would
error out on previously accepted assembler.

llvm-svn: 228109

llvm-svn: 228108

llvm-svn: 228107