Commits · e7a306310b0bfbd97cdce8f77686b6453fc76bca · Roger Ferrer / llvm-epi · GitLab

Dec 30, 2022
- [AMDGPU][GFX11] Correct tied src2 of v_fmac_f16_e64 · e7a30631
  Dmitry Preobrazhensky authored Dec 30, 2022
  e7a30631
- [ScheduleDAG] Support REQ_SEQUENCE unscheduling · 98265db8
  Filipp Zhinkin authored Dec 27, 2022
  98265db8
- [RISCV] Use SUB instead of XOR in lowerShiftLeftParts/lowerShiftRightParts./ · a63b7247
  Craig Topper authored Dec 29, 2022
  a63b7247
- [RISCV] RISCVDAGToDAGISel::selectShiftMask to shift by (sub size-1, X). · 7cd72585
  Craig Topper authored Dec 29, 2022
  7cd72585
- AMDGPU/clang: Remove target features from address space test builtins · e630d9b2
  Matt Arsenault authored Nov 28, 2022
  e630d9b2
- DAG: Prevent store value forwarding to distinct addrspace load · 0ec51a46
  Dmitry Borisenkov authored Dec 29, 2022
  0ec51a46
- [RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to bypass adds with constant. · e50976e5
  Craig Topper authored Dec 29, 2022
  e50976e5
Dec 29, 2022
- [NFC][Codegen][X86] zero_extend_vector_inreg.ll: add SSE4.2 runline · c823517e
  Roman Lebedev authored Dec 30, 2022
  
  c823517e
- [DAGCombiner] Try to partition ISD::EXTRACT_VECTOR_ELT to accomodate it's ISD::BUILD_VECTOR users · 248567a3
  Roman Lebedev authored Dec 29, 2022
  248567a3
- [TargetLowering] Teach BuildUDIV to take advantage of leading zeros in the dividend. · 8abd7008
  Craig Topper authored Dec 29, 2022
  8abd7008
- [BPF] Use SectionForGlobal() for section names computation in BTF · ed068386
  Eduard Zingerman authored Dec 29, 2022
  ed068386
- [RISCV] Add fmin/fmax scalar instructions to isAssociativeAndCommutative · af5dd270
  Hsiangkai Wang authored Dec 23, 2022
  af5dd270
- [RISCV] Add integer scalar instructions to isAssociativeAndCommutative · 002005e6
  Hsiangkai Wang authored Dec 22, 2022
  002005e6
- [RISCV] Add Svpbmt extension support. · bd9c0f08
  Yeting Kuo authored Dec 27, 2022
  bd9c0f08
- [RISCV] Add SH1ADD/SH2ADD/SH3ADD to RISCVDAGToDAGISel::hasAllNBitUsers. · 0e9855c1
  Craig Topper authored Dec 28, 2022
  
  0e9855c1
- [RISCV] Prefer ADDI over ORI if the known bits are disjoint. · 79d6e9c7
  Craig Topper authored Dec 28, 2022
  79d6e9c7
- [NFC][Codegen][X86] Add exhaustive-ish test coverage for ZERO_EXTEND_VECTOR_INREG · 778a7df5
  Roman Lebedev authored Dec 29, 2022
  778a7df5
- [RISCV] Fix mistakes in fixed-vectors-vreductions-mask.ll command lines. NFC · 9b59207a
  Craig Topper authored Dec 28, 2022
  9b59207a
- [RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasAllNBitUsers. · 6357b637
  Craig Topper authored Dec 28, 2022
  
  6357b637
Dec 28, 2022
- [RISCV] Support SRLI in hasAllNBitUsers. · cdf09ce7
  Craig Topper authored Dec 28, 2022
  cdf09ce7
- [XRay] Fix Hexagon sled version · 27751bed
  Fangrui Song authored Dec 28, 2022
  27751bed
- [X86] Emit RIP-relative access to local function in PIC medium code model · 82be8a1d
  Thomas Köppe authored Dec 28, 2022
  82be8a1d
- [NVPTX] Emit .noreturn directive · fa023e0f
  Pavel Kopyl authored Dec 28, 2022
  fa023e0f
- Fix failure of ldst-16-byte.mir · d0068087
  Qiu Chaofan authored Dec 28, 2022
  
  d0068087
- [PowerPC] Enable track-subreg-liveness by default · 0ad57bf2
  Qiu Chaofan authored Dec 28, 2022
  0ad57bf2
Dec 27, 2022
- [AArch64][MachineScheduler] Set no side effect for movprfx · c69d8390
  zhongyunde authored Dec 28, 2022
  c69d8390
Dec 26, 2022
- [DAGCombine] `combineShuffleToZeroExtendVectorInReg()`: widen shuffle elements... · c4f815d7
  Roman Lebedev authored Dec 26, 2022
  c4f815d7
- [NFC][X86] Add some tests that can be matched as ZERO_EXTEND_VECTOR_INREG · cc051b07
  Roman Lebedev authored Dec 27, 2022
  
  cc051b07
- [DAG] `combineShuffleToZeroExtendVectorInReg()`: try to match w/ commuted operands · e26e7ed6
  Roman Lebedev authored Dec 26, 2022
  e26e7ed6
- [AArch64] Custom lower `ISD::ZERO_EXTEND_VECTOR_INREG` · 83288f80
  Roman Lebedev authored Dec 26, 2022
  83288f80
- [DAGCombiner] Add a most basic `combineShuffleToZeroExtendVectorInReg()` · 62fc5f16
  Roman Lebedev authored Dec 25, 2022
  62fc5f16
- [NFC][AArch64] Add a few vector shuffle tests that should be `zip1` · 46458aad
  Roman Lebedev authored Dec 26, 2022
  46458aad
- [TwoAddressInstruction] Constrain RegClass when processing a statepoint · 821a5958
  Danila Malyutin authored Dec 23, 2022
  821a5958
- [LoongArch][test] Regenerate checks for the ghc-cc.ll test case · 77fad4c3
  WANG Xuerui authored Dec 26, 2022
  77fad4c3
- [LoongArch] Add GHC Calling Convention · 389079c8
  Lin Runze authored Dec 26, 2022
  389079c8
- [RISCV] Implement assembler support for XTHeadVdot · 54752f3f
  Jojo R authored Nov 09, 2022
  54752f3f
Dec 25, 2022
- [SPIRV] support __spirv_Load/Store builtin functions · 0b0224bc
  Ilia Diachkov authored Dec 26, 2022
  0b0224bc
- Revert "[RISCV] Enable the LocalStackSlotAllocation pass support." · dfec6f7e
  Craig Topper authored Dec 25, 2022
  dfec6f7e
Dec 24, 2022
- [NFC][Codegen][X86] Autogenerate check lines in shift-i256.ll · ec99bf24
  Roman Lebedev authored Dec 24, 2022
  
  ec99bf24
- [NFC][Codegen][AVR] Make shift.ll autogenerate-able · 3bb5ddd1
  Roman Lebedev authored Dec 24, 2022
  
  3bb5ddd1