Commits · 07ed62b7d5514937a50b4af4feaa1969911d142e · Lorenzo Albano / LLVM bpEVL · GitLab

Mar 19, 2021
- [RISCV] Spilling for Zvlsseg registers. · aa8d33a6
  Hsiangkai Wang authored Mar 15, 2021
  aa8d33a6
Mar 16, 2021
- [RISCV] Support clang -fpatchable-function-entry && GNU function attribute... · 6ab89279
  Fangrui Song authored Mar 16, 2021
  6ab89279
Mar 09, 2021
- [RISCV] Make the hasStdExtM() check in RISCVInstrInfo::getVLENFactoredAmount... · 478317fb
  Craig Topper authored Mar 09, 2021
  478317fb
Feb 17, 2021
- [RISCV] Spilling for RISC-V V extension. (2nd version) · a3c783db
  Hsiangkai Wang authored Jan 08, 2021
  a3c783db
- [RISCV] Frame handling for RISC-V V extension. · 5a31a673
  Hsiangkai Wang authored Jan 08, 2021
  5a31a673
Feb 08, 2021
- [RISCV] Make scalable vector FMA commutable for register allocation. · b7b4f4cb
  Craig Topper authored Feb 08, 2021
  b7b4f4cb
Jan 27, 2021
- [RISCV] Move RISCVVPseudosTable from RISCVBaseInfo.h to RISCVInstrInfo.h. NFC · 58aa049b
  Craig Topper authored Jan 27, 2021
  58aa049b
Jan 14, 2021
- [RISCV] Merge Utils library into MCTargetDesc · 387d3c24
  Craig Topper authored Jan 14, 2021
  387d3c24
Dec 21, 2020
- [Target] Use llvm::erase_if (NFC) · 966f1431
  Kazu Hirata authored Dec 20, 2020
  
  966f1431
Dec 15, 2020
- [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions. · a6805a0e
  Hsiangkai Wang authored Dec 11, 2020
  a6805a0e
Dec 04, 2020
- [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump · ad923edf
  Craig Topper authored Dec 04, 2020
  ad923edf
Dec 03, 2020
- [RISCV] Support Zfh half-precision floating-point extension. · f7bc7c29
  Hsiangkai Wang authored Jul 03, 2020
  f7bc7c29
Nov 19, 2020
- [RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot · 6b0fc1f3
  Craig Topper authored Nov 18, 2020
  6b0fc1f3
Nov 03, 2020
- [RISCV] Only return DestSourcePair from isCopyInstrImpl for registers · 7601a217
  Jessica Clarke authored Nov 03, 2020
  7601a217
Sep 21, 2020
- [RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl() · 8cf6778d
  Alex Richardson authored Sep 21, 2020
  8cf6778d
Aug 27, 2020
- [RISC-V] fmv.s/fmv.d should be as cheap as a move · 5ba4d036
  Alex Richardson authored Aug 25, 2020
  5ba4d036
- [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move · 2259ce8c
  Alex Richardson authored Aug 25, 2020
  2259ce8c
Aug 17, 2020
- [RISCV] Indirect branch generation in position independent code · 5f9ecc5d
  Sam Elliott authored Aug 17, 2020
  5f9ecc5d
Jul 15, 2020
- [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos · 3382c243
  Jessica Clarke authored Jul 15, 2020
  3382c243
Jul 14, 2020
- [RISCV] Fix isStoreToStackSlot · 0cbdd2a8
  Roger Ferrer authored Jul 14, 2020
  0cbdd2a8
Apr 22, 2020
- [MachineOutliner] Teach outliner to set live-ins · 1a78b0bd
  Eli Friedman authored Apr 21, 2020
  1a78b0bd
Feb 03, 2020
- [NFC] unsigned->Register in storeRegTo/loadRegFromStack · 5c8ba508
  Simon Moll authored Feb 03, 2020
  5c8ba508
Jan 31, 2020
- [RISCV] Implement jump pseudo-instruction · 24cba331
  Luís Marques authored Jan 31, 2020
  24cba331
Jan 21, 2020
- Update spelling of {analyze,insert,remove}Branch in strings and comments · 020041d9
  Krzysztof Parzyszek authored Jan 21, 2020
  020041d9
Jan 17, 2020
- [Transforms][RISCV] Remove a "using namespace llvm" from an include file. Fix... · caee9603
  Craig Topper authored Jan 16, 2020
  caee9603
Dec 19, 2019
- [RISCV] Enable the machine outliner for RISC-V · a116f28a
  lewis-revill authored Dec 19, 2019
  a116f28a
Dec 17, 2019
- Fix assertion failure in getMemOperandWithOffsetWidth · 870f39d3
  Kristof Beyls authored Dec 11, 2019
  870f39d3
- [RISCV] Added isCompressibleInst() to estimate size in getInstSizeInBytes() · d7af86bd
  Ana Pazos authored Dec 16, 2019
  d7af86bd
Dec 09, 2019
- [RISCV] Machine Operand Flag Serialization · c20930a7
  Sam Elliott authored Dec 09, 2019
  c20930a7
Nov 11, 2019
- Use MCRegister in copyPhysReg · e6c9a9af
  Matt Arsenault authored Nov 11, 2019
  
  e6c9a9af
Nov 05, 2019
- [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook · 0d47c7ab
  Luís Marques authored Nov 05, 2019
  0d47c7ab
Oct 16, 2019
- [RISCV] Add MachineInstr immediate verification · 1893f9a4
  Luis Marques authored Oct 16, 2019
  1893f9a4
Sep 13, 2019
- [RISCV] Support stack offset exceed 32-bit for RV64 · a49a16dd
  Shiva Chen authored Sep 13, 2019
  a49a16dd
- Revert "[RISCV] Support stack offset exceed 32-bit for RV64" · ea530ba3
  Shiva Chen authored Sep 13, 2019
  ea530ba3
- [RISCV] Support stack offset exceed 32-bit for RV64 · eaa230fe
  Shiva Chen authored Sep 13, 2019
  eaa230fe
Aug 16, 2019
- [RISCV] Convert registers from unsigned to Register · fa06e958
  Luis Marques authored Aug 16, 2019
  fa06e958
Aug 13, 2019
- [risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM · 3836874d
  Daniel Sanders authored Aug 12, 2019
  3836874d
Jul 18, 2019
- [RISCV] Don't acccess an invalidated iterator in RISCVInstrInfo::removeBranch · ad73a436
  Alex Bradbury authored Jul 18, 2019
  ad73a436
Jun 26, 2019
- [RISCV] Add pseudo instruction for calls with explicit register · cf748813
  Lewis Revill authored Jun 26, 2019
  cf748813
Jun 19, 2019
- [RISCV] Add lowering of global TLS addresses · 39263ac5
  Lewis Revill authored Jun 19, 2019
  39263ac5